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| ispMACH 5000B Family TM Discontinued Product (PCN #02-06). Contact Rochester Electronics for Availability. www.latticesemi.com/sales/discontinueddevicessales.cfm 2.5V In-System Programmable SuperWIDETM High Density PLDs September 2003 Data Sheet Features High Speed Logic Implementation * SuperWIDE 68-input logic block * Up to 35 product terms per output * Single-level Global Routing Pool (GRP) Easy System Integration * 2.5V power supply * Hot socketing * Input pull-up, pull-down or Bus-keeper (Pin-by-pin selectable) * Open drain capability * Macrocell-based power management * IEEE 1149.1 Boundary Scan testable * IEEE 1532 compliant In-System Programmable (ISPTM) sysIOTM Capability * * * * * * * * * * * * LVCMOS 1.8, 2.5 and 3.3 LVTTL SSTL 2 (I and II) SSTL 3 (I and II) CTT 3.3, CTT 2.5 HSTL (I and III) PCI 3.3 GTL+ AGP-1X LVDS (clock input) LVPECL (clock input) Programmable drive strength ispMACH 5000B Introduction The ispMACH 5000B represents the next generation of Lattice's SuperWIDE CPLD architecture. Through their wide 68-input blocks, these devices give significantly improved speed performance for typical designs over architectures with a lower number of inputs. In addition to the unique benefits of the SuperWIDE architecture, the ispMACH 5000B provides sysIO capability to provide support for a variety of advanced I/O standards. The ispMACH 5000B devices consist of multiple SuperWIDE 68-input, 32-macrocell Generic Logic Blocks (GLBs) interconnected by a single-level routing system referred to as the Global Routing Pool (GRP). Figure 1 shows the ispMACH 5000B block diagram. Together, the GLBs and the GRP allow designers to create large designs in a single device without compromising performance. Ease of Design * Product term sharing * Extensive clocking and OE capability Broad Device Offering * 128 to 512 macrocells * 92 to 256 I/Os * 128 to 484 pins/balls in TQFP, PQFP and fpBGA packages * Commercial and industrial temperature ranges Table 1. ispMACH 5000B Family Selection Guide ispMACH 5128B Macrocells User I/O Options tPD (ns) tS - Set-up with 0 Hold (ns) tCO (ns) fMAX (MHz) Supply Voltage (V) Package 128 92 3.0 1.7 2.2 275 2.5 128-pin TQFP ispMACH 5256B 256 92/144 4.0 2.1 2.7 250 2.5 128-pin TQFP 208-pin PQFP 256-ball fpBGA ispMACH 5384B 384 156/186 4.0 2.1 2.7 250 2.5 208-pin PQFP 256-ball fpBGA ispMACH 5512B 512 156/196/256 4.5 2.5 2.8 200 2.5 208-pin PQFP 256-ball fpBGA 484-ball fpBGA www.latticesemi.com 1 5kb_11.1 Lattice Semiconductor Figure 1. Functional Block Diagram I/O Bank 0 ispMACH 5000B Family Data Sheet Discontinued Product (PCN #02-06). Contact Rochester Electronics for Availability. www.latticesemi.com/sales/discontinueddevicessales.cfm I/O Bank 3 VCCO0 VREF0 GCLK0 Generic Logic Block Global Routing Pool Generic Logic Block VCCO3 VREF3 GCLK3 TDI TDO TMS TCK TOE GCLK1 VCCO1 VREF1 Generic Logic Block Generic Logic Block GCLK2 VCCO2 VREF2 RESETB GOE1 GOE2 I/O Bank 1 I/O Bank 2 The GLB has 68 inputs coming from the GRP and contains 163 product terms. These product terms form groups of five product term clusters, which feed the product term sharing array and the macrocell directly. The ispMACH 5000B allows up to 35 product terms to be connected to a single macrocell via the Product Term Sharing Array. The macrocell is designed to provide flexible clocking and control functionality with the capability to select between global, product term, and block-level resources. The outputs of the macrocells are fed back into the switch matrices and, if required, the sysIO cell. All I/Os in the ispMACH 5000B family are sysIO capable, which are split into four banks. Each bank has a separate I/O power supply and reference voltage. The sysIO cells allow operation with a wide range of today's emerging interface standards. Within a bank, inputs can be set to a variety of standards providing the reference voltage requirements of the chosen standards are compatible. Within each bank, the outputs can be set to differing standards providing the I/O power supply requirements of the chosen standard are compatible. Support for this wide range of standards allows designers to achieve significantly higher board-level performance compared to the more traditional LVCMOS standards. Table 1 shows the key attributes and packages for the ispMACH5000B devices. ispMACH 5000B Architecture The ispMACH 5000B Family of In-System Programmable (ISPTM) high density programmable logic devices is based on Generic Logic Blocks (GLBs) and a global routing pool (GRP) structure interconnecting the GLBs. Outputs from the GLBs drive the GRP. Enhanced switching resources are provided to allow signals in the GRP to drive any or all of the GLBs. This mechanism allows fast, efficient connections across the entire device. Figure 1 shows the basic ispMACH 5000B architecture. Generic Logic Block Each GLB contains 32 macrocells and a fully populated, programmable AND-array with 160 logic product terms and three GLB-level control product terms. The GLB has 68 inputs from the GRP, which are available in both true 2 Lattice Semiconductor ispMACH 5000B Family Data Sheet and complement form for every product term. The three control product terms are used for shared reset, clock and output enable functions. Discontinued Product (PCN #02-06). Contact Rochester Electronics for Availability. www.latticesemi.com/sales/discontinueddevicessales.cfm AND-Array The programmable AND-array consists of 68 inputs and 163 output product terms. The 68 inputs from the GRP are used to form 136 lines in the AND-array (true and complement of the inputs). Each line in the array can be connected to any of the 163 output product terms via a wired AND. Each of the 160 logic product terms feed the DualOR Array with the remaining three control product terms feeding the Shared PT Clock, Shared PT Reset, and Shared PT OE. Every set of five product terms from the 160 logic product terms forms a product term cluster starting with PT0. There is one product term cluster for every macrocell in the GLB. In addition to the three control product terms, the first, third, fourth and fifth product terms of each cluster can be used as a PTOE (output macrocells only), PT Clock, PT Preset and PT Reset, respectively. Figure 2 is a graphical representation of the AND-Array. Figure 2. ispMACH 5000B AND-Array In[0] In[66] In[67] PT0 PT1 PT2 PT3 PT4 Cluster 0 PT155 PT156 PT157 Cluster 31 PT158 PT159 PT160 Shared clock PT161 Shared reset PT162 Shared OE Note: Indicates programmable fuse. Dual-OR Array There are two OR gates per macrocell in the GLB. These OR gates are referred to as the PTSA OR gate and the PTSA-Bypass OR gate. The PTSA-Bypass OR gate receives its five inputs from the combination of product terms associated with the product term cluster. The PTSA-Bypass OR gate feeds the macrocell directly for fast narrow logic. The PTSA OR gate receives its inputs from the combination of product terms associated with the product term cluster. Figure 3 shows the Dual-OR Array. 3 Lattice Semiconductor Figure 3. ispMACH 5000B Dual-OR Array From PT0 ispMACH 5000B Family Data Sheet Discontinued Product (PCN #02-06). Contact Rochester Electronics for Availability. www.latticesemi.com/sales/discontinueddevicessales.cfm PT OE To I/O Block From PT1 PTSA Bypass To Macrocell From PT2 n To PTSA PT Clock To Macrocell From PT3 PT Preset To Macrocell From PT4 PT Reset To Macrocell Product Term Sharing Array The Product Term Sharing Array (PTSA) consists of 32 inputs from the Dual-OR Array and 32 outputs directly to the macrocells. Each output is the OR term of any combination of the seven PTSA OR terms connected to that output. Every Nth macrocell is connected to N-3, N-2, N-1, N, N+1, N+2, and N+3 PTSA OR terms via a programmable connection. Figure 4 shows the graphical representation of the PTSA. Figure 4. ispMACH 5000B PTSA PTSA OR 0 PTSA OR 1 PTSA OR 2 PTSA OR 3 Macrocell 0 Macrocell 1 Macrocell 2 PTSA OR 29 PTSA OR 30 PTSA OR 31 Macrocell 29 Macrocell 30 Macrocell 31 4 Lattice Semiconductor Macrocell ispMACH 5000B Family Data Sheet Discontinued Product (PCN #02-06). Contact Rochester Electronics for Availability. www.latticesemi.com/sales/discontinueddevicessales.cfm The 32 registered macrocells in the GLB are driven by the 32 outputs from the PTSA or the PTSA bypass. Each macrocell contains a programmable XOR gate, a programmable register/latch flip-flop and the necessary clocks and control logic to allow combinatorial or registered operation. The macrocells each have two outputs, which can be fed to the GRP and I/O cell. This dual or concurrent output capability from the macrocell gives efficient use of the hardware resources. One output can be a registered function for example, while the other output can be an unrelated combinatorial function. A direct register input from the I/O cell facilitates efficient use of the macrocell to construct high-speed input registers. Macrocell registers can be clocked from one of several global or product term clocks available on the device. A global and product term clock enable is also provided, eliminating the need to gate the clock to the macrocell registers directly. Reset and preset for the macrocell register is provided from both global and product term signals. The macrocell register can be programmed to operate as a D-type register or a D-type latch. Figure 5 is a graphical representation of the ispMACH 5000B macrocell. Figure 5. ispMACH 5000B Macrocell From GRP PT OE to I/O Block From I/O Cell PTSA Bypass Output to I/O Block D PTSA PT Clock Clk En GRP R/L Shared PT Clock CLK0 CLK1 CLK2 CLK3 68 Q Speed/ Power Clk P R PT Preset PT Reset Shared PT Reset Global Reset AND Array Dual-OR Array Macrocell I/O Cell The ispMACH 5000B I/O cell provides a high degree of flexibility. It includes the sysIO feature and an enhanced output enable MUX for optimal performance both on- and off-chip. The sysIO feature allows I/O cells to be configured to different I/O standards, drive strengths and slew rates. The enhanced output enable MUX provides up to 14 different output enable choices per I/O cell. The I/O cell contains an output enable (OE) MUX, a programmable tri-state output buffer, a programmable input buffer, a programmable pull-up resistor, a programmable pull-down resistor and a programmable bus-friendly latch. The I/O cell receives its input from its associated macrocell. The I/O cell has a feedback line to its associated macrocell and a direct path to the GRP. The output enable (OE) MUX selects the OE signal per I/O cell. The inputs to the OE MUX are the four shared PTOE signals, PTOE, the two GOE signals. The OE MUX also has the ability to choose either the true or inverse of 5 Lattice Semiconductor ispMACH 5000B Family Data Sheet each of these signals. The output of the OE MUX goes through a logical AND with the TOE signal to allow easy tristating of the outputs for testing purposes. The four Shared PTOE signals are derived from PT163 of each GLB. The PTOE signal is derived from the first product term in each macrocell cluster, which is directly routed to the OE MUX. Therefore, every I/O cell can have a different OE signal. Figure 6 is a graphical representation of the I/O cell. Figure 6. ispMACH 5000B I/O Cell Global PTOE 0 Global PTOE 1 Global PTOE 2 Global PTOE 3 PTOE GOE0 GOE1 TOE Data Output from Macrocell Output Buffer (VCCO independent for open drain outputs) CMOS/TTL Input Buffer (VREF independent) VCCO to all other I/Os in bank Discontinued Product (PCN #02-06). Contact Rochester Electronics for Availability. www.latticesemi.com/sales/discontinueddevicessales.cfm VCC for whole chip GND I/O Pad Data Input to Routing Data Input to Macrocell + - VREF dependent Input Buffer VREF to all other I/Os in bank sysIO Capability The ispMACH 5000B devices are divided into four sysIO banks, where each bank is capable of supporting 14 different I/O standards. Each sysIO bank has its own I/O supply voltage (VCCO), reference voltage (VREF), and termination voltage (VTT, as applicable), resources allowing each bank complete independence from the others. Each I/O within a bank is individually configurable consistent with the VCCO and VREF settings. In addition, each I/O has individually configurable drive strength, weak pull-up, weak pull-down or a bus-friendly latch. Table 2 lists the sysIO standards with the typical values for VCCO, VREF and VTT. The TOE and JTAG pins of the ispMACH 5000B device are the only pins that do not have sysIO capabilities. These pins support the 2.5V LVTTL and LVCMOS standards. There are three classes of I/O interface standards implemented in the ispMACH 5000B devices. The first is the un-terminated, single-ended interface. It includes the 3.3V LVTTL standard along with the 1.8V, 2.5V and 3.3V LVCMOS interface standards. Additionally, PCI and AGP-1X are all subsets of this type of interface. The second type of interface implemented is the terminated, single-ended interface standard. This group of interfaces includes different versions of SSTL and HSTL interfaces along with CTT, GTL+ and single-ended LVPECL. Use of these particular I/O interfaces requires an additional VREF signal. At the system level a termination voltage, VTT, is also required. Typically an output will be terminated to VTT at the receiving end of the transmission line it is driving. The final type of interfaces implemented are the differential standards LVDS and LVPECL. These interfaces are implemented on clock pins only. When using one of the differential standards, a pair of global clock pins (GCLK0 and GCLK1 or GCLK2 and GCLK3) are combined to create a single clock signal. 6 Lattice Semiconductor ispMACH 5000B Family Data Sheet For more information on the sysIO capability, please refer to technical note number TN1000, sysIO Design and Usage Guidelines available on the Lattice web site at www.latticesemi.com. Table 2. ispMACH 5000B Supported I/O Standards sysIO Standard LVTTL LVCMOS 3.3 LVCMOS 2.5 LVCMOS 1.8 PCI 3.3 AGP-1X SSTL3, Class I, II SSTL2, Class I, II CTT 3.3 CTT 2.5 HSTL, Class I HSTL, Class III GTL+ VCCO 3.3V 3.3V 2.5V 1.8V 3.3V 3.3V 3.3V 2.5V 3.3V 2.5V 1.5V 1.5V N/A VREF N/A N/A N/A N/A N/A N/A 1.5V 1.25V 1.5V 1.25V 0.75V 0.9 1.0V VTT N/A N/A N/A N/A N/A N/A 1.5V 1.25V 1.5V 1.25V 0.75V 0.75V 1.5V Discontinued Product (PCN #02-06). Contact Rochester Electronics for Availability. www.latticesemi.com/sales/discontinueddevicessales.cfm GLB Clock Distribution The ispLSI 5000B family has four dedicated clock input pins: GCLK0-GCLK3. These feed the Global Clock MUX, which generates the four global clock signals (CLK0-CLK3). The global clock MUX allows a variety of combinattions of complementary forms of the clock to be used within the device. Additionally, the ispMACH 5000B clock distribution network offers a differential pair of clock inputs into the global clock MUX for added flexibility. Figure 7 shows the global clock MUX. The global clock pins are arranged in two pairs, GCLK0 and GCLK1 signals are in one pair and GCLK2 and GCLK3 signals are in the other pair. The pins are arranged on the die such that each pair of external clock signals can generate one internal clock from either side of the die when used in differential inputs. This arrangement allows the clock pins to be used either as four single ended clock signals or two differential (LVPECL or LVDS) clock signal. Both polarities of the clock are available to drive the internal clock distribution networks. 7 Lattice Semiconductor Figure 7. ispMACH 5000B Global Clock MUX GCLK0 VREF0 + - ispMACH 5000B Family Data Sheet Discontinued Product (PCN #02-06). Contact Rochester Electronics for Availability. www.latticesemi.com/sales/discontinueddevicessales.cfm CLK0 GCLK1 VREF1 VREF2 GCLK2 + - CLK1 - + CLK2 VREF3 GCLK3 - + CLK3 Power Management The ispMACH 5000B devices provide unique power management controls. The device has two power settings, high power and low power, on a per node basis. Low power consumption is approximately 50% of high power consumption with a timing delay adder (tLP) to the routing delay of the low power node. Each node can be configured as either high power or low power. However, care should be taken when sharing product terms between nodes with different power settings. The ispMACH 5000B devices also have a power-off feature for product terms that are not used. By default, any product term that is not used is configured as such. This allows the device to operate at minimal power consumption without affecting the timing of the design. For further information on power management, please refer to technical note number TN1023, Power Estimation in ispMACH 5000B Devices available on the Lattice web site at www.latticesemi.com. IEEE 1149.1-Compliant Boundary Scan Testability All ispMACH 5000B devices have boundary scan cells and are compliant to the IEEE 1149.1 standard. This allows functional testing of the circuit board on which the device is mounted through a serial scan path that can access all critical logic nodes. Internal registers are linked internally, allowing test data to be shifted in and loaded directly onto test nodes, or test node data to be captured and shifted out for verification. In addition, these devices can be linked into a board-level serial scan path for more board-level testing. sysIO Quick Configuration To facilitate the most efficient board test, the physical circuit configuration of the I/O cells must be set before running any continuity tests. As these tests are fast, by nature, the overhead and time that is required for configuration of the I/Os should be minimal so that board test time is minimized. The ispMACH 5000B family of devices supports this by offering the user the ability to quickly configure the I/O standard supported by the sysIO cells. This quick configuration takes milliseconds to complete, whereas it takes seconds for the entire device to be programmed. Lattice's ispVMTM System programming software can either perform the quick configuration through the PC parallel port, or can generate the ATE or test vectors necessary for a third-party test system. IEEE 1532-Compliant In-System Programming In-system programming of devices provides a number of significant benefits including rapid prototyping, lower inventory levels, higher quality, and the ability to make in-field modifications. All ispMACH 5000B devices provide in-system programmability through their Boundary Scan Test Access Port. This capability has been implemented in a manner 8 Lattice Semiconductor ispMACH 5000B Family Data Sheet that ensures that the port remains compliant to the IEEE 1532 standard. By using IEEE 1532 as the communication interface through which ISP is achieved, customers get the benefit of a standard, well-defined interface. The ispMACH 5000B devices can be programmed across the commercial temperature and voltage range. The PCbased Lattice software facilitates in-system programming of ispMACH 5000B devices. The software takes the JEDEC file output produced by the design implementation software, along with information about the JTAG chain, and creates a set of vectors that are used to drive the JTAG chain. The software can use these vectors to drive a JTAG chain via the parallel port of a PC. Alternatively, the software can output files in formats understood by common automated test equipment. This equipment can then be used to program ispMACH 5000B devices during the testing of a circuit board. Discontinued Product (PCN #02-06). Contact Rochester Electronics for Availability. www.latticesemi.com/sales/discontinueddevicessales.cfm Security Scheme A programmable security scheme is provided on the ispMACH 5000B devices as a deterrent to unauthorized copying of the array configuration patterns. Once programmed, this security prevents readback of the programmed pattern by a device programmer, securing proprietary designs from competitors. The security scheme also prevents programming and verification. The entire device must be erased in order to reset the security scheme. Hot Socketing The ispMACH 5000B devices are well suited for those applications that require hot socketing capability. Hot socketing a device requires that the device, when powered down, can tolerate active signals on the I/Os and inputs without being damaged. Additionally, it requires that the effects of the powered-down device be minimal on active signals. Density Migration The ispMACH 5000B family has been designed to ensure that different density devices in the same package have the same pin-out. Furthermore, the architecture ensures a high success rate when performing design migration from lower density parts to higher density parts. In many cases, it is possible to shift a lower utilization design targeted for a high density device to a lower density device. However, the exact details of the final resource utilization will impact the likely success in each case. 9 Lattice Semiconductor ispMACH 5000B Family Data Sheet Absolute Maximum Ratings1, 2, 3 Supply Voltage VCC . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 4.05V Output Supply Voltage VCCO . . . . . . . . . . . . . . . . . . -0.5 to 4.05V Input Voltage Applied4 . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 4.05V Tri-state Output Voltage Applied. . . . . . . . . . . . . . . . -0.5 to 4.05V Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . -65 to 150C Junction Temperature (Tj) with Power Applied . . . . . -55 to 130C 1. Stress above those listed under the "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. 2. Compliance with Lattice Thermal Management document is required. 3. All voltages referenced to GND. 4. Overshoot and Undershoot of -2V to (VIHMAX +2) volts is permitted for a duration of < 20ns. Discontinued Product (PCN #02-06). Contact Rochester Electronics for Availability. www.latticesemi.com/sales/discontinueddevicessales.cfm Recommended Operating Conditions Symbol VCC TJ Supply Voltage Junction Temperature (Commercial) Junction Temperature (Industrial) Parameter Min 2.3 0 -40 Max 2.7 90 105 Units V C C Erase Reprogram Specifications Parameter Erase/Reprogram Cycle Min 1,000 Max -- Units Cycles Hot Socketing Characteristics1,2,3 Symbol IDK Parameter Input or I/O Leakage Current Condition 0 VIN VIH (MAX) VIH (MAX) VIN 3.6V Min -- -- Typ -- -- Max +/- 100 +/- 100 Units A A 1. Insensitive to sequence of VCC and VCCO. However, assumes monotonic rise / fall rates for VCC and VCCO. 2. LVTTL, LVCMOS only 3. 0 VCC VCC (MAX), 0 VCCO VCCO (MAX) 10 Lattice Semiconductor ispMACH 5000B Family Data Sheet DC Electrical Characteristics Over Recommended Operating Conditions Symbol IIL, IIH1, 2 IDK IPU2 IPD 2 Discontinued Product (PCN #02-06). Contact Rochester Electronics for Availability. www.latticesemi.com/sales/discontinueddevicessales.cfm Parameter Input I/O Input I/O I/O Weak Pull-up Resistor Current Condition 0V VIN VCC 0V VIN VCCO VCC VIN 3.6V VCCO VIN 3.6V 0V VIN 1.7V 1.7V < VIN 2.0V VIN = VIL (MAX) VIN = 1.7V VIN = 2.0V 0V VIN 3.6V 0V VIN 3.6V No Output Loading VCCO = 3.3V Min -- -- -- -- -30 -15 30 30 -30 -15 -- -- VIL (MAX) -- -- -- -- -- -- Typ -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 8 10 10 Max +/- 10 +/- 10 +/- 100 +/- 100 -150 -150 150 -- -- -- 150 -150 VIH (MIN) 10 10 10 -- -- -- Units A A A A A A A A A A A A V mA mA mA pf pf pf I/O Weak Pull-down Resistor Current VIL (MAX) VIN VIH (MAX) Bus Hold Low Sustaining Current Bus Hold High Sustaining Current Bus Hold Low Overdrive Current Bus Hold High Overdrive Current Bus Hold Trip Points IBHLS2 IBHHS2 IBHLO VBHT 2 IBHHO2 ICCO3, 4, 5, 6 I/O Supply Current No Output Loading VCCO = 2.5V No Output Loading VCCO = 1.8V C1 C2 C3 I/O Capacitance3 Clock Capacitance 3 VCC = 2.5V, VIO = 0 to 3.6V VCC = 2.5V, VCLOCK = 0 to 3.6V VCC = 2.5V, VGLOBAL = 0 to 3.6V Global Input Capacitance3 1. Input or I/O leakage current is measured with the pin configured as an input or as an I/O with the output driver tri-stated. It is not measured with the output driver active. Bus maintenance circuits are disabled. 2. Only available for LVCMOS and LVTTL standards. 3. TA = 25C, f = 1.0MHz. 4. Device configured with 16-bit counters. 5. ICC varies with specific device configuration and operating frequency. 6. Per bank. Supply Current Symbol ispMACH 5128B ICC1, 2, 3 ICC1, 2, 3 ICC1, 2, 3 ICC1, 2, 3 Operating Power Supply Current Operating Power Supply Current Operating Power Supply Current Operating Power Supply Current VCCO = 2.5V VCCO = 2.5V VCCO = 2.5V VCCO = 2.5V -- -- -- -- 83 130 216 270 -- -- -- -- mA mA mA mA ispMACH 5256B ispMACH 5384B ispMACH 5512B 1. TA = 25C, f = 1.0MHz. 2. Device configured with 16-bit counters. 3. ICC varies with specific device configuration and operating frequency. Parameter Condition Min Typ Max Units 11 Lattice Semiconductor ispMACH 5000B Family Data Sheet sysIO Recommended Operating Conditions VCCO (V) Standard LVTTL LVCMOS 3.3 LVCMOS 2.5 LVCMOS 1.8 PCI 3.3 AGP-1X SSTL 3, Class I, II SSTL 2, Class I, II CTT 3.3 CTT 2.5 HSTL GTL+ 1. Software default setting. 1 Discontinued Product (PCN #02-06). Contact Rochester Electronics for Availability. www.latticesemi.com/sales/discontinueddevicessales.cfm VREF (V) Max 3.6 3.6 2.7 1.95 3.6 3.45 3.6 2.7 3.6 2.7 1.6 3.6 Min -- -- -- -- -- -- 1.3 1.15 1.35 1.35 0.68 0.882 Max -- -- -- -- -- -- 1.7 1.35 1.65 1.65 0.9 1.122 Min 3.0 3.0 2.3 1.65 3.0 3.15 3.0 2.3 3.0 2.3 1.4 1.4 12 Lattice Semiconductor ispMACH 5000B Family Data Sheet sysIO DC Electrical Characteristics Over Recommended Operating Conditions Input/Output Standard LVCMOS 3.3 VIL Min (V) -0.3 Max (V) 0.8 Min (V) 2.0 VIH Max (V) 3.6 VOL Max (V) 0.4 0.4 0.2 0.4 0.4 0.2 LVCMOS 1.8 PCI 3.3 AGP-1X SSTL3 class I SSTL3 class II SSTL2 class I SSTL2 class II CTT 3.3 CTT 2.5 HSTL class I HSTL class III GLT+ -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 0.68 1.08 1.08 VREF-0.2 VREF-0.2 VREF-0.18 VREF-0.18 VREF-0.2 VREF-0.2 VREF-0.1 VREF-0.1 VREF-0.2 1.07 1.5 1.5 VREF+0.2 VREF+0.2 VREF+0.18 VREF+0.18 VREF+0.2 VREF+0.2 VREF+0.1 VREF+0.1 VREF+0.2 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 0.4 0.2 0.1VCCO 0.1VCCO 0.7 0.5 0.54 0.35 VREF-0.4 VREF-0.4 0.4 0.4 0.6 VOH Min (V) 2.4 2.4 VCCO - 0.2 VCCO - 0.4 VCCO - 0.4 VCCO - 0.2 VCCO-0.4 VCCO - 0.2 0.9VCCO 0.9VCCO VCCO - 1.1 VCCO - 0.9 VCCO - 0.62 VCCO - 0.43 VREF + 0.4 VREF + 0.4 VCCO - 0.4 VCCO - 0.4 N/A IOL2 (mA) 20, 16, 12, 8, 5.33, 4 20 0.1 8 16, 12, 5.33, 4 0.1 12, 8, 5.33, 4 0.1 1.5 1.5 8 16 7.6 15.2 8 8 8 24 36 IOH2 (mA) -20, -16, -12, -8, -5.33 -4 20 0.1 -8 -16, -12, -5.33, -4 -0.1 -12, -8, -5.33, -4 -0.1 -0.5 -0.5 -8 -16 -7.6 -15.2 -8 -8 -8 -8 N/A Discontinued Product (PCN #02-06). Contact Rochester Electronics for Availability. www.latticesemi.com/sales/discontinueddevicessales.cfm LVTTL LVCMOS 2.5 LVCMOS 2.5 1 -0.3 -0.3 -0.3 0.8 0.7 0.7 2.0 1.7 1.7 3.6 3.6 3.6 1. Software default setting 2. The average DC current drawn by I/Os between adjacent bank GND connections, or between the last GND in an I/O bank and the end of the I/O bank, as shown in the logic signals connection table, shall not exceed 96mA. sysIO Differential Input DC Electrical Characteristics and Operating Conditions Symbol VINP . VINM VTHD VIL1 VIH1 Parameter LVDS Input voltage LVDS Differential input threshold LVPECL Input Voltage Low LVPECL Input Voltage High VCCIO = 3.3V VCCIO = 3.0 to 3.6V VCCIO = 3.3V Test Conditions -- -- VCCIO = 3.0 to 3.6V Min 0V +/- 100mV VCCIO -1.81V 1.49V VCCIO -1.17V 2.14V Max 2.4V -- VCCIO -1.48V 1.83V VCCIO -0.88V 2.42V 1. VCCIO is in 3.3V range. 13 Lattice Semiconductor ispMACH 5000B Family Data Sheet ispMACH 5128B External Switching Characteristics Over Recommended Operating Conditions -3 Parameter tPD tPD_PTSA tS tS_PTSA tSIR tH tH_PTSA tHIR tCO tR tRW tPTEN/DIS tGPTEN/DIS tGOE/DIS tCW tGW tWIR fMAX4 fMAX (Ext.) Description Propagation delay GLB register setup time before clock, 5-PT bypass GLB register setup time before clock GLB register setup time before clock, input register path, 5-PT bypass GLB register hold time before clock, 5-PT bypass GLB register hold time before clock GLB register hold time before clock, input reg.path GLB register clock-to-output delay External reset pin to output delay Reset pulse duration Input to output local product term output enable/disable Input to output global product term output enable/disable Global OE input to output enable/disable Clock pulse duration Global gate width low (for low transparent) or high (for high transparent) Input register clock width, high or low Clock frequency with internal feedback Clock frequency with external feedback, 1/(tS_PTSA + tCO) 1, 2, 3 Discontinued Product (PCN #02-06). Contact Rochester Electronics for Availability. www.latticesemi.com/sales/discontinueddevicessales.cfm -5 Max. 3.0 3.8 2.2 2.5 4.0 4.2 2.5 Min. 3.0 4.0 2.5 0.0 0.0 0.0 3.5 2.2 2.2 2.2 180 142 225 Max. 5.0 6.5 3.0 5.0 6.0 7.0 3.7 5.0 6.5 3.5 0.0 0.0 0.0 5.0 2.5 2.5 2.5 150 95 200 -75 Min. Max. 7.5 9.0 4.0 7.5 8.5 10.0 5.5 6.5 8.5 5.0 0.0 0.0 0.0 6.5 2.8 2.8 2.8 110 71 175 -10 Min. Max. Units 10.0 12.0 5.5 10.0 10.0 12.0 7.5 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz MHz MHz Min. 1.7 2.2 2.0 0.0 0.0 0.0 3.0 1.3 1.3 1.3 275 227 350 Data propagation delay, 5-PT bypass fMAX (Tog.) Clock frequency max toggle 1. 2. 3. 4. Timing v.1.0 Timing Numbers are based on default LVCMOS 2.5V, 8mA I/O buffers. Use timing adjusters provided to calculate timing for other standards. Measured using standard switching circuit, assuming global routing loading of 1, worst case PTSA loading, CLK0, 1 output switching and high speed AND array. Pulse widths and clock widths less than minimum will cause unknown behavior. Standard 16-bit counter using GRP feedback. 14 Lattice Semiconductor ispMACH 5000B Family Data Sheet ispMACH 5256B External Switching Characteristics Over Recommended Operating Conditions -4 Parameter tPD tPD_PTSA tS tS_PTSA tSIR tH tH_PTSA tHIR tCO tR tRW tPTEN/DIS tGPTEN/DIS tGOE/DIS tCW tGW tWIR fMAX4 fMAX (Ext.) Description Propagation delay GLB register setup time before clock, 5-PT bypass GLB register setup time before clock GLB register setup time before clock, input register path, 5-PT bypass GLB register hold time before clock, 5-PT bypass GLB register hold time before clock GLB register hold time before clock, input reg.path GLB register clock-to-output delay External reset pin to output delay Reset pulse duration Input to output local product term output enable/disable Input to output global product term output enable/disable Global OE input to output enable/disable Clock pulse duration Global gate width low (for low transparent) or high (for high transparent) Input register clock width, high or low Clock frequency with internal feedback Clock frequency with external feedback, 1/(tS_PTSA + tCO) 1, 2, 3 Discontinued Product (PCN #02-06). Contact Rochester Electronics for Availability. www.latticesemi.com/sales/discontinueddevicessales.cfm -5 Max. 4.0 4.8 2.7 3.8 5.0 5.5 3.4 Min. 3.0 4.0 2.5 0.0 0.0 0.0 3.5 2.2 2.2 2.2 180 142 225 6.0 7.0 3.7 Max. 5.0 6.5 3.0 5.0 5.0 6.5 3.5 0.0 0.0 0.0 5.0 2.5 2.5 2.5 150 95 200 -75 Min. Max. 7.5 9.0 4.0 7.5 8.5 10.0 5.5 6.5 8.5 5.0 0.0 0.0 0.0 6.5 2.8 2.8 2.8 110 71 175 -10 Min. Max. Units 10.0 12.0 5.5 10.0 10.0 12.0 7.5 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz MHz MHz Min. 2.1 2.7 1.9 0.0 0.0 0.0 3.0 1.5 1.5 1.5 250 185 333 Data propagation delay, 5-PT bypass fMAX (Tog.) Clock frequency max toggle 1. 2. 3. 4. Timing v.1.3 Timing Numbers are based on default LVCMOS 2.5V, 8mA I/O buffers. Use timing adjusters provided to calculate timing for other standards. Measured using standard switching circuit, assuming global routing loading of 1, worst case PTSA loading, CLK0, 1 output switching and high speed AND array. Pulse widths and clock widths less than minimum will cause unknown behavior. Standard 16-bit counter using GRP feedback. 15 Lattice Semiconductor ispMACH 5000B Family Data Sheet ispMACH 5384B External Switching Characteristics Over Recommended Operating Conditions -4 Parameter tPD tPD_PTSA tS tS_PTSA tSIR tH tH_PTSA tHIR tCO tR tRW tPTEN/DIS tGPTEN/DIS tGOE/DIS tCW tGW tWIR fMAX4 fMAX (Ext.) Description Propagation delay GLB register setup time before clock, 5-PT bypass GLB register setup time before clock GLB register setup time before clock, input register path, 5-PT bypass GLB register hold time before clock, 5-PT bypass GLB register hold time before clock GLB register hold time before clock, input reg.path GLB register clock-to-output delay External reset pin to output delay Reset pulse duration Input to output local product term output enable/ disable Input to output global product term output enable/disable Global OE input to output enable/disable Clock pulse duration Global gate width low (for low transparent) or high (for high transparent) Input register clock width, high or low Clock frequency with internal feedback Clock frequency with external feedback, 1/(tS_PTSA+tCO) 1, 2, 3 Discontinued Product (PCN #02-06). Contact Rochester Electronics for Availability. www.latticesemi.com/sales/discontinueddevicessales.cfm -5 Max. 4.0 4.8 2.7 3.8 5.0 5.5 3.4 Min. 3.0 4.0 2.5 0.0 0.0 0.0 3.5 2.2 2.2 2.2 180 142 225 Max. 5.0 6.5 3.0 5.0 6.0 7.0 3.7 5.0 6.5 3.5 0.0 0.0 0.0 5.0 2.5 2.5 2.5 150 95 200 -75 Min. Max. 7.5 9.0 4.0 7.5 8.5 10.0 5.5 6.5 8.5 5.0 0.0 0.0 0.0 6.5 2.8 2.8 2.8 110 71 175 -10 Min. Max. Units 10.0 12.0 5.5 10.0 10.0 12.0 7.5 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz MHz MHz Min. 2.1 2.7 1.9 0.0 0.0 0.00 3.0 1.5 1.5 1.5 250 185 333 Data propagation delay, 5-PT bypass fMAX (Tog.) Clock frequency max toggle 1. 2. 3. 4. Timing v.1.0 Timing Numbers are based on default LVCMOS 2.5V, 8mA I/O buffers. Use timing adjusters provided to calculate timing for other standards. Measured using standard switching circuit, assuming global routing loading of 1, worst case PTSA loading, CLK0, 1 output switching and high speed AND array. Pulse widths and clock widths less than minimum will cause unknown behavior. Standard 16-bit counter using GRP feedback. 16 Lattice Semiconductor ispMACH 5000B Family Data Sheet ispMACH 5512B External Switching Characteristics Over Recommended Operating Conditions -45 Parameter tPD tPD_PTSA tS tS_PTSA tSIR tH tH_PTSA tHIR tCO tR tRW tPTEN/DIS Description Propagation delay GLB register setup time before clock, 5-PT bypass GLB register setup time before clock GLB register setup time before clock, input register path, 5-PT bypass GLB register hold time before clock, 5-PT bypass GLB register hold time before clock GLB register hold time before clock, input reg.path GLB register clock-to-output delay External reset pin to output delay Reset pulse duration Input to output local product term output enable/ disable 1, 2, 3 Discontinued Product (PCN #02-06). Contact Rochester Electronics for Availability. www.latticesemi.com/sales/discontinueddevicessales.cfm -75 Min. 5.0 6.5 3.5 0.0 0.0 0.0 5.0 2.5 2.5 2.5 150 95 200 Max. 7.5 9.0 4.0 7.5 8.5 10.0 5.5 4.5 5.3 2.8 4.2 5.5 6.3 3.5 6.5 8.5 5.0 0.0 0.0 0.0 6.5 2.8 2.8 2.8 110 71 175 -10 Min. Max. 10.0 12.0 5.5 10.0 10.0 12.0 7.5 7.5 -12 Min. Max. Units 12.0 15.0 6.5 12.0 12.0 15.0 9.0 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz MHz MHz Min. 2.5 3.1 1.7 0.0 0.0 0.0 3.0 2.0 2.0 2.0 200 169 250 Max. Data propagation delay, 5-PT bypass 10.5 5.5 0.0 0.0 0.0 8.0 3.3 3.3 3.3 90 58 150 tGPTEN/DIS Input to output global product term output enable/disable tGOE/DIS tCW tGW tWIR fMAX4 Global OE input to output enable/disable Clock pulse duration Global gate width low (for low transparent) or high (for high transparent) Input register clock width, high or low Clock frequency with internal feedback fMAX (Ext.) Clock frequency with external feedback, 1/(tS_PTSA + tCO) fMAX (Tog.) Clock frequency max toggle 1. 2. 3. 4. Timing v.1.1 Timing Numbers are based on default LVCMOS 2.5V, 8mA I/O buffers. Use timing adjusters provided to calculate timing for other standards. Measured using standard switching circuit, assuming global routing loading of 1, worst case PTSA loading, CLK0 and 1 output switching and high speed AND array. Pulse widths and clock widths less than minimum will cause unknown behavior. Standard 16-bit counter using GRP feedback. 17 Lattice Semiconductor ispMACH 5000B Family Data Sheet Timing Model The task of determining the timing through the ispLSI 5000B family, just as any CPLD, is relatively simple. The timing model provided in Figure 8 shows the specific delay paths. Once the implementation of a given function is determined either conceptually or from the design tool report file, the delay path of the function can easily be derived from the timing model. The design tool reports the timing delays based on the same timing model for a particular design. Note that the internal timing parameters are given for reference only and are not tested. The external timing parameters are tested and guaranteed for every device. Figure 8. ispMACH 5000B Timing Model Routing/ GLB Delays From Feedback tPDb Feedback tPDi tROUTE IN Discontinued Product (PCN #02-06). Contact Rochester Electronics for Availability. www.latticesemi.com/sales/discontinueddevicessales.cfm tFBK tBUF tEN tDIS tIOO In/Out Delays tIN tIOI tINREG tGCLK_IN tIOI tBLA tLP tPTSA DATA OUT Q CLK tPTCLK tBCLK CE tPTSR tBSR tRST tIOI tGPTOE tPTOE OE S/R MC Reg RST Register/ Latch Delays tGOE tIOI Control Delays In/Out Delays Note: Italicized parameters are delay adders above and beyond default conditions (i.e. GRP load of one GLB, CLK0, high-speed AND Array and VCC I/O option). 18 Lattice Semiconductor ispMACH 5000B Family Data Sheet ispMACH 5128B Internal Timing Parameters1 Over Recommended Operating Conditions -3 Parameter In/Out Delays tIN tGCLK_IN tGOE tBUF tEN tDIS tRST tROUTE tPTSA tPDb tPDi tINREG tFBK tS tS_PT tSL_PT tH tCOi tCES tCEH tSL tHL tGOi tPDLi tSRi tSRR tBCLK tPTCLK tBSR tPTSR tGPTOE tPTOE Input Buffer Delay Global Clock Input Buffer Delay Global OE Pin Delay Delay through Output Buffer Output Enable Time Output Disable Time Global Rest Pin Delay Delay through GRP Product Term Sharing Array 5-PT Bypass Propogation Delay Macrocell Propogation Delay Input Buffer to Macrocell Register Delay Internal Feedback Delay D-Register Setup Time (Global Clock) D-Register Setup Time (Product Term Clock) Latch Setup Time (Product Term Clock) D-Register Hold Time Register Clock to Output/Feedback Mux Time Clock Enable Setup Time Clock Enable Hold Time Latch Setup Time Latch Hold Time Latch Gate to Output/Feedback Mux Time Propogation Delay through Transparent Latch to Output/Feedback Mux Asynchronous Reset or Set to Output/Feedback MUX Delay Asynchronous Reset or Set Recovery Delay GLB PT Clock Delay Macrocell PT Clock Delay Block PT Set/Reset Delay Macrocell PT Set/Reset Delay Global PT OE Delay Macrocell PT OE Delay 0.20 0.20 0.20 1.50 3.30 0.20 0.20 1.50 1.50 0.30 1.00 1.60 0.50 0.90 0.90 1.20 1.60 1.10 0.60 0.30 2.50 0.00 0.70 0.70 0.50 0.80 1.70 1.50 1.20 0.80 1.40 1.20 0.30 0.20 0.20 2.70 4.30 0.40 0.30 2.70 2.70 0.60 1.50 2.60 0.80 1.10 1.10 2.20 2.50 2.10 1.10 0.50 3.10 0.00 0.70 0.60 0.50 2.00 2.40 2.10 1.70 1.10 2.80 1.80 4.70 0.50 0.70 4.30 4.00 0.70 0.70 0.70 4.30 2.00 1.40 3.00 1.80 2.50 2.50 2.70 2.60 2.60 1.10 0.00 2.20 0.00 0.80 0.80 0.50 3.00 2.80 2.40 1.90 1.20 2.90 1.40 5.00 0.60 0.90 5.60 6.00 0.90 0.90 0.90 5.60 2.40 1.90 4.40 2.50 3.10 3.10 3.60 3.70 3.40 1.40 0.00 3.60 0.00 1.10 1.60 0.50 3.90 3.20 2.70 2.10 1.30 2.80 0.80 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Description Min. Max. Min. -5 Max. -75 Min. Max. -10 Min. Max. Units Discontinued Product (PCN #02-06). Contact Rochester Electronics for Availability. www.latticesemi.com/sales/discontinueddevicessales.cfm Routing Delays Register/Latch Delays Control Delays Timing v.1.0 1. Internal Timing Parameters are not tested and are for reference only. Refer to Timing Model in this data sheet for further details. 19 Lattice Semiconductor ispMACH 5000B Family Data Sheet ispMACH 5256B Internal Timing Parameters1 Over Recommended Operating Conditions -4 Parameter In/Out Delays tIN tGCLK_IN tGOE tBUF tEN tDIS tRST tROUTE tPTSA tPDb tPDi tINREG tFBK tS tS_PT tSL_PT tH tCOi tCES tCEH tSL tHL tGOi tPDLi tSRi tSRR tBCLK tPTCLK tBSR tPTSR tGPTOE tPTOE Input Buffer Delay Global Clock Input Buffer Delay Global OE Pin Delay Delay through Output Buffer Output Enable Time Output Disable Time Global Rest Pin Delay Delay through GRP Product Term Sharing Array 5-PT Bypass Propogation Delay Macrocell Propogation Delay Input Buffer to Macrocell Register Delay Internal Feedback Delay D-Register Setup Time (Global Clock) D-Register Setup Time (Product Term Clock) Latch Setup Time (Product Term Clock) D-Register Hold Time Register Clock to Output/Feedback Mux Time Clock Enable Setup Time Clock Enable Hold Time Latch Setup Time Latch Hold Time Latch Gate to Output/Feedback Mux Time Propogation Delay through Transparent Latch to Output/Feedback Mux Asynchronous Reset or Set to Output/Feedback MUX Delay Asynchronous Reset or Set Recovery Delay GLB PT Clock Delay Macrocell PT Clock Delay Block PT Set/Reset Delay Macrocell PT Set/Reset Delay Global PT OE Delay Macrocell PT OE Delay 0.30 0.30 0.30 1.80 3.90 0.30 0.30 1.80 2.00 0.40 1.20 2.40 1.00 1.00 1.00 1.30 1.80 1.40 0.80 0.20 2.40 0.00 0.50 0.60 0.50 1.50 2.00 1.80 1.50 1.00 2.30 1.80 0.30 0.20 0.20 2.70 4.30 0.40 0.30 2.70 2.70 0.60 1.50 2.60 0.80 1.10 1.10 2.20 2.50 2.10 1.10 0.50 3.10 0.00 0.70 0.60 0.50 2.00 2.40 2.10 1.70 1.10 2.80 1.80 4.70 0.50 0.70 4.30 4.00 0.70 0.70 0.70 4.30 2.00 1.40 3.00 1.80 2.50 2.50 2.70 2.60 2.60 1.10 0.00 2.20 0.00 0.80 0.80 0.50 3.00 2.80 2.40 1.90 1.20 2.90 1.40 5.00 0.60 0.90 5.60 6.00 0.90 0.90 0.90 5.60 2.40 1.90 4.40 2.50 3.10 3.10 3.60 3.70 3.40 1.40 0.00 3.60 0.00 1.10 1.60 0.50 3.90 3.20 2.70 2.10 1.30 2.80 0.80 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Description Min. Max. Min. -5 Max. -75 Min. Max. -10 Min. Max. Units Discontinued Product (PCN #02-06). Contact Rochester Electronics for Availability. www.latticesemi.com/sales/discontinueddevicessales.cfm Routing Delays Register/Latch Delays Control Delays Timing v.1.3 1. Internal Timing Parameters are not tested and are for reference only. Refer to Timing Model in this data sheet for further details. 20 Lattice Semiconductor ispMACH 5000B Family Data Sheet ispMACH 5384B Internal Timing Parameters1 Over Recommended Operating Conditions -4 Parameter In/Out Delays tIN tGCLK_IN tGOE tBUF tEN tDIS tRST tROUTE tPTSA tPDb tPDi tINREG tFBK tS tS_PT tSL_PT tH tCOi tCES tCEH tSL tHL tGOi tPDLi tSRi tSRR tBCLK tPTCLK tBSR tPTSR tGPTOE tPTOE Input Buffer Delay Global Clock Input Buffer Delay Global OE Pin Delay Delay through Output Buffer Output Enable Time Output Disable Time Global Rest Pin Delay Delay through GRP Product Term Sharing Array 5-PT Bypass Propogation Delay Macrocell Propogation Delay Input Buffer to Macrocell Register Delay Internal Feedback Delay D-Register Setup Time (Global Clock) D-Register Setup Time (Product Term Clock) Latch Setup Time (Product Term Clock) D-Register Hold Time Register Clock to Output/Feedback MUX Time Clock Enable Setup Time Clock Enable Hold Time Latch Setup Time Latch Hold Time Latch Gate to Output/Feedback Mux Time Propogation Delay through Transparent Latch to Output/Feedback Mux Asynchronous Reset or Set to Output/Feedback MUX Delay Asynchronous Reset or Set Recovery Delay GLB PT Clock Delay Macrocell PT Clock Delay Block PT Set/Reset Delay Macrocell PT Set/Reset Delay Global PT OE Delay Macrocell PT OE Delay 0.30 0.30 0.30 1.80 3.90 0.30 0.30 1.80 2.00 0.40 1.20 2.40 1.00 1.00 1.00 1.30 1.80 1.40 0.80 0.20 2.40 0.00 0.50 0.60 0.50 1.50 2.00 1.80 1.50 1.00 2.30 1.80 0.30 0.20 0.20 2.70 4.30 0.40 0.30 2.70 2.70 0.60 1.50 2.60 0.80 1.10 1.10 2.20 2.50 2.10 1.10 0.50 3.10 0.00 0.70 0.60 0.50 2.00 2.40 2.10 1.70 1.10 2.80 1.80 4.70 0.50 0.70 4.30 4.00 0.70 0.70 0.70 4.30 2.00 1.40 3.00 1.80 2.50 2.50 2.70 2.60 2.60 1.10 0.00 2.20 0.00 0.80 0.80 0.50 3.00 2.80 2.40 1.90 1.20 2.90 1.40 5.00 0.60 0.90 5.60 6.00 0.90 0.90 0.90 5.60 2.40 1.90 4.40 2.50 3.10 3.10 3.60 3.70 3.40 1.40 0.00 3.60 0.00 1.10 1.60 0.50 3.90 3.20 2.70 2.10 1.30 2.80 0.80 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Description Min. Max. Min. -5 Max. -75 Min. Max. -10 Min. Max. Units Discontinued Product (PCN #02-06). Contact Rochester Electronics for Availability. www.latticesemi.com/sales/discontinueddevicessales.cfm Routing Delays Register/Latch Delays Control Delays Timing v.1.0 1. Internal Timing Parameters are not tested and are for reference only. Refer to Timing Model in this data sheet for further details. 21 Lattice Semiconductor ispMACH 5000B Family Data Sheet ispMACH 5512B Internal Timing Parameters1 Over Recommended Operating Conditions -45 Parameter In/Out Delays tIN tGCLK_IN tGOE tBUF tEN tDIS tRST tROUTE tPTSA tPDb tPDi tINREG tFBK tS tS_PT tSL_PT tH tCOi tCES tCEH tSL tHL tGOi tPDLi tSRi tSRR tBCLK tPTCLK tBSR tPTSR tGPTOE tPTOE Input Buffer Delay Global Clock Input Buffer Delay Global OE Pin Delay Delay through Output Buffer Output Enable Time Output Disable Time Global Rest Pin Delay Delay through GRP Product Term Sharing Array 5-PT Bypass Propogation Delay Macrocell Propogation Delay Input Buffer to Macrocell Register Delay Internal Feedback Delay D-Register Setup Time (Global Clock) D-Register Setup Time (Product Term Clock) Latch Setup Time (Product Term Clock) D-Register Hold Time Register Clock to Output/Feedback Mux Time Clock Enable Setup Time Clock Enable Hold Time Latch Setup Time Latch Hold Time Latch Gate to Output/Feedback Mux Time Propogation Delay through Transparent Latch to Output/Feedback Mux Asynchronous Reset or Set to Output/Feedback Mux Delay Asynchronous Reset or Set Recovery Delay GLB PT Clock Delay Macrocell PT Clock Delay Block PT Set/Reset Delay Macrocell PT Set/Reset Delay Global PT OE Delay Macrocell PT OE Delay 0.10 0.10 0.10 2.40 4.10 0.30 0.10 2.40 2.30 0.30 1.50 2.50 0.60 1.00 1.00 1.90 2.50 1.70 1.10 0.20 2.80 0.00 0.70 0.60 0.50 1.70 2.20 2.00 1.60 1.10 2.50 1.70 4.70 0.50 0.70 4.30 4.00 0.70 0.70 0.70 4.30 2.00 1.40 3.00 1.80 2.50 2.50 2.70 2.60 2.60 1.10 0.00 2.20 0.00 0.80 0.80 0.50 3.00 2.80 2.40 1.90 1.20 2.90 1.40 5.00 0.60 0.90 5.60 6.00 0.90 0.90 0.90 5.60 2.40 1.90 4.40 2.50 3.10 3.10 3.60 3.70 3.40 1.40 0.00 3.60 0.00 1.10 1.60 0.50 3.90 3.20 2.70 2.10 1.30 2.80 0.80 5.00 0.60 0.80 5.60 7.50 0.80 1.40 1.40 6.70 3.20 2.50 5.50 2.80 3.50 3.50 4.90 4.10 4.90 1.90 0.00 4.00 0.00 1.20 1.60 0.50 4.30 3.60 3.00 2.30 1.40 4.20 1.20 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Description Min. Max. -75 Min. Max. -10 Min. Max. -12 Min. Max. Units Discontinued Product (PCN #02-06). Contact Rochester Electronics for Availability. www.latticesemi.com/sales/discontinueddevicessales.cfm Routing Delays Register/Latch Delays Control Delays Timing v.1.1 1. Internal Timing Parameters are not tested and are for reference only. Refer to Timing Model in this data sheet for further details. 22 Lattice Semiconductor ispMACH 5000B Family Data Sheet Discontinued Product (PCN #02-06). Contact Rochester Electronics for Availability. www.latticesemi.com/sales/discontinueddevicessales.cfm ispMACH 5128B Timing Adders Adder Type tLP tIOI Input Adders LVCMOS18_in LVCMOS25_in LVCMOS33_in PCI_in AGP_1X_in SSTL3_I_in SSTL3_II_in SSTL2_I_in SSTL2_II_in CTT33_in CTT25_in HSTL_I_in HSTL_III_in GTL+_in LVDS_in LVPECL_D_in tIDO Output Adders Slow Slew LVCMOS18_4mA_out LVCMOS18_5mA_out LVCMOS18_8mA_out tEN, tBUF tEN, tDIS, tBUF tEN, tDIS, tBUF tEN, tDIS, tBUF Output configured for slow slew rate Output configured as 1.8V & 4mA Buffer Output configured as 1.8V & 5.33mA Buffer Output configured as 1.8V & 8mA Buffer Output configured as 1.8V & 12mA Buffer Output configured as 2.5V & 4mA Buffer Output configured as 2.5V & 5.33mA Buffer 1.50 0.80 0.50 0.10 -0.10 0.50 0.20 1.50 0.80 0.50 0.10 -0.10 0.50 0.20 1.50 0.80 0.50 0.10 -0.10 0.50 0.20 1.50 0.80 0.50 0.10 -0.10 0.50 0.20 ns ns ns ns ns ns ns tIN, tGCLK_IN, tRST, tGOE tIN, tGCLK_IN, tRST, tGOE tIN, tGCLK_IN, tRST, tGOE tIN, tGCLK_IN, tRST, tGOE tIN, tGCLK_IN, tRST, tGOE tIN, tGCLK_IN, tRST, tGOE tIN, tGCLK_IN, tRST, tGOE tIN, tGCLK_IN, tRST, tGOE tIN, tGCLK_IN, tRST, tGOE tIN, tGCLK_IN, tRST, tGOE tIN, tGCLK_IN, tRST, tGOE tIN, tGCLK_IN, tRST, tGOE tIN, tGCLK_IN, tRST, tGOE tIN, tGCLK_IN, tRST, tGOE tGCLK_IN tGCLK_IN Using LVCMOS1.8 standard Using LVCMOS2.5 standard Using LVCMOS3.3 standard Using PCI standard Using AGP-1X standard Using SSTL3_I standard Using SSTL3_II standard Using SSTL2_I standard Using SSTL2_II standard Using CTT3.3 standard Using CTT2.5 standard Using HSTL_I standard Using HSTL_III standard Using GTL+ standard Using LVDS standard Using LVDS differential standard 0.40 0.00 0.20 1.00 1.00 0.90 0.90 0.90 0.90 0.90 0.90 1.00 1.00 1.00 0.50 1.10 0.40 0.00 0.20 1.00 1.00 0.90 0.90 0.90 0.90 0.90 0.90 1.00 1.00 1.00 0.50 1.10 0.40 0.00 0.20 1.00 1.00 0.90 0.90 0.90 0.90 0.90 0.90 1.00 1.00 1.00 0.50 1.10 0.40 0.00 0.20 1.00 1.00 0.90 0.90 0.90 0.90 0.90 0.90 1.00 1.00 1.00 0.50 1.10 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Base Parameter tROUTE -4 Description Low Power Adder 1.00 -5 1.00 -75 1.00 -10 1.00 ns Min. Max. Min. Max. Min. Max. Min. Max. Units LVCMOS18_12mA_out tEN, tDIS, tBUF LVCMOS25_4mA_out LVCMOS25_5mA_out tEN, tDIS, tBUF tEN, tDIS, tBUF Note: Open drain timing is the same as corresponding LVCMOS timing. Timing v.1.0 23 Lattice Semiconductor ispMACH 5000B Family Data Sheet ispMACH 5128B Timing Adders (Cont.) Adder Type LVCMOS25_8mA_out Base Parameter tEN, tDIS, tBUF -4 Description Output configured as 2.5V & 8mA Buffer Output configured as 2.5V & 12mA Buffer Output configured as 2.5V & 16mA Buffer Output configured as 3.3V & 4mA Buffer Output configured as 3.3V & 5.33mA Buffer Output configured as 3.3V & 8mA Buffer Output configured as 3.3V & 12mA Buffer Output configured as 3.3V & 16mA Buffer Output configured as 3.3V & 20mA Buffer Using PCI standard Using AGP-1X standard Using SSTL3_I standard Using SSTL3_II standard Using SSTL2_I standard Using SSTL2_II standard Using CCT3.3 standard Using CCT2.5 standard Using HSTL_I standard Using HSTL_III standard Using GTL+ standard -5 -75 -10 Min. Max. Min. Max. Min. Max. Min. Max. Units 0.00 -0.10 -0.20 0.80 0.20 0.00 -0.10 -0.10 -0.20 -0.20 -0.20 0.50 0.10 0.50 -0.10 0.80 0.20 0.10 0.40 2.00 0.00 0.20 0.20 0.20 0.00 -0.10 -0.20 0.80 0.20 0.00 -0.10 -0.10 -0.20 -0.20 -0.20 0.50 0.10 0.50 -0.10 0.80 0.20 0.10 0.40 2.00 0.00 0.20 0.20 0.20 0.00 -0.10 -0.20 0.80 0.20 0.00 -0.10 -0.10 -0.20 -0.20 -0.20 0.50 0.10 0.50 -0.10 0.80 0.20 0.10 0.40 2.00 0.00 0.20 0.20 0.20 0.00 -0.10 -0.20 0.80 0.20 0.00 -0.10 -0.10 -0.20 -0.20 -0.20 0.50 0.10 0.50 -0.10 0.80 0.20 0.10 0.40 2.00 0.00 0.20 0.20 0.20 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Discontinued Product (PCN #02-06). Contact Rochester Electronics for Availability. www.latticesemi.com/sales/discontinueddevicessales.cfm LVCMOS25_12mA_out tEN, tDIS, tBUF LVCMOS25_16mA_out tEN, tDIS, tBUF LVCMOS33_4A_out LVCMOS33_5mA_out LVCMOS33_8mA_out tEN, tDIS, tBUF tEN, tDIS, tBUF tEN, tDIS, tBUF LVCMOS33_12mA_out tEN, tDIS, tBUF LVCMOS33_16mA_out tEN, tDIS, tBUF LVCMOS33_20mA_out tEN, tDIS, tBUF PCI_out AGP_1X_out SSTL3_I_out SSTL3_II_out SSTL2_I_out SSTL2_II_out CTT33_out CTT_25_out HSTL_I_out HSTL_III_out GTL+_out tIOI Input Adders CLK0 CLK1 CLK2 CLK3 tGCLK_IN tGCLK_IN tGCLK_IN tGCLK_IN tEN, tDIS, tBUF tEN, tDIS, tBUF tEN, tDIS, tBUF tEN, tDIS, tBUF tEN, tDIS, tBUF tEN, tDIS, tBUF tEN, tDIS, tBUF tEN, tDIS, tBUF tEN, tDIS, tBUF tEN, tDIS, tBUF tEN, tDIS, tBUF Note: Open drain timing is the same as corresponding LVCMOS timing. Timing v.1.0 24 Lattice Semiconductor ispMACH 5000B Family Data Sheet ispMACH 5128B Timing Adders (Cont). -4 Adder Type 1 2 3 tROUTE tROUTE tROUTE Base Parameter tBLA Additional Block Loading Adders 0.10 0.10 0.20 0.10 0.10 0.20 0.10 0.10 0.20 0.10 0.10 0.20 ns ns ns -5 -75 -10 Min. Max. Min. Max. Min. Max. Min. Max. Units Discontinued Product (PCN #02-06). Contact Rochester Electronics for Availability. www.latticesemi.com/sales/discontinueddevicessales.cfm Note: Open drain timing is the same as corresponding LVCMOS timing. Timing v.1.0 25 Lattice Semiconductor ispMACH 5000B Family Data Sheet Discontinued Product (PCN #02-06). Contact Rochester Electronics for Availability. www.latticesemi.com/sales/discontinueddevicessales.cfm ispMACH 5256B Timing Adders Adder Type tLP tIOI Input Adders LVCMOS18_in LVCMOS25_in LVCMOS33_in PCI_in AGP_1X_in SSTL3_I_in SSTL3_II_in SSTL2_I_in SSTL2_II_in CTT33_in CTT25_in HSTL_I_in HSTL_III_in GTL+_in LVDS_in LVPECL_D_in tIDO Output Adders Slow Slew LVCMOS18_4mA_out LVCMOS18_5mA_out LVCMOS18_8mA_out tEN, tBUF tEN, tDIS, tBUF tEN, tDIS, tBUF tEN, tDIS, tBUF Output configured for slow slew rate Output configured as 1.8V & 4mA Buffer Output configured as 1.8V & 5.33mA Buffer Output configured as 1.8V & 8mA Buffer Output configured as 1.8V & 12mA Buffer Output configured as 2.5V & 4mA Buffer Output configured as 2.5V & 5.33mA Buffer 1.50 0.80 0.50 0.10 -0.10 0.50 0.20 1.50 0.80 0.50 0.10 -0.10 0.50 0.20 1.50 0.80 0.50 0.10 -0.10 0.50 0.20 1.50 0.80 0.50 0.10 -0.10 0.50 0.20 ns ns ns ns ns ns ns tIN, tGCLK_IN, tRST, tGOE tIN, tGCLK_IN, tRST, tGOE tIN, tGCLK_IN, tRST, tGOE tIN, tGCLK_IN, tRST, tGOE tIN, tGCLK_IN, tRST, tGOE tIN, tGCLK_IN, tRST, tGOE tIN, tGCLK_IN, tRST, tGOE tIN, tGCLK_IN, tRST, tGOE tIN, tGCLK_IN, tRST, tGOE tIN, tGCLK_IN, tRST, tGOE tIN, tGCLK_IN, tRST, tGOE tIN, tGCLK_IN, tRST, tGOE tIN, tGCLK_IN, tRST, tGOE tIN, tGCLK_IN, tRST, tGOE tGCLK_IN tGCLK_IN Using LVCMOS1.8 standard Using LVCMOS2.5 standard Using LVCMOS3.3 standard Using PCI standard Using AGP-1X standard Using SSTL3_I standard Using SSTL3_II standard Using SSTL2_I standard Using SSTL2_II standard Using CTT3.3 standard Using CTT2.5 standard Using HSTL_I standard Using HSTL_III standard Using GTL+ standard Using LVDS standard Using LVDS differential standard 0.40 0.00 0.20 1.00 1.00 0.90 0.90 0.90 0.90 0.90 0.90 1.00 1.00 1.00 0.50 1.10 0.40 0.00 0.20 1.00 1.00 0.90 0.90 0.90 0.90 0.90 0.90 1.00 1.00 1.00 0.50 1.10 0.40 0.00 0.20 1.00 1.00 0.90 0.90 0.90 0.90 0.90 0.90 1.00 1.00 1.00 0.50 1.10 0.40 0.00 0.20 1.00 1.00 0.90 0.90 0.90 0.90 0.90 0.90 1.00 1.00 1.00 0.50 1.10 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Base Parameter tROUTE -4 Description Low Power Adder 1.00 -5 1.00 -75 1.00 -10 1.00 ns Min. Max. Min. Max. Min. Max. Min. Max. Units LVCMOS18_12mA_out tEN, tDIS, tBUF LVCMOS25_4mA_out LVCMOS25_5mA_out tEN, tDIS, tBUF tEN, tDIS, tBUF Note: Open drain timing is the same as corresponding LVCMOS timing. Timing v.1.3 26 Lattice Semiconductor ispMACH 5000B Family Data Sheet ispMACH 5256B Timing Adders (Cont.) Adder Type LVCMOS25_8mA_out Base Parameter tEN, tDIS, tBUF -4 Description Output configured as 2.5V & 8mA Buffer Output configured as 2.5V & 12mA Buffer Output configured as 2.5V & 16mA Buffer Output configured as 3.3V & 4mA Buffer Output configured as 3.3V & 5.33mA Buffer Output configured as 3.3V & 8mA Buffer Output configured as 3.3V & 12mA Buffer Output configured as 3.3V & 16mA Buffer Output configured as 3.3V & 20mA Buffer Using PCI standard Using AGP-1X standard Using SSTL3_I standard Using SSTL3_II standard Using SSTL2_I standard Using SSTL2_II standard Using CCT3.3 standard Using CCT2.5 standard Using HSTL_I standard Using HSTL_III standard Using GTL+ standard -5 -75 -10 Min. Max. Min. Max. Min. Max. Min. Max. Units 0.00 -0.10 -0.20 0.80 0.20 0.00 -0.10 -0.10 -0.20 -0.20 -0.20 0.50 0.10 0.50 -0.10 0.80 0.20 0.10 0.40 2.00 0.00 0.20 0.20 0.20 0.00 -0.10 -0.20 0.80 0.20 0.00 -0.10 -0.10 -0.20 -0.20 -0.20 0.50 0.10 0.50 -0.10 0.80 0.20 0.10 0.40 2.00 0.00 0.20 0.20 0.20 0.00 -0.10 -0.20 0.80 0.20 0.00 -0.10 -0.10 -0.20 -0.20 -0.20 0.50 0.10 0.50 -0.10 0.80 0.20 0.10 0.40 2.00 0.00 0.20 0.20 0.20 0.00 -0.10 -0.20 0.80 0.20 0.00 -0.10 -0.10 -0.20 -0.20 -0.20 0.50 0.10 0.50 -0.10 0.80 0.20 0.10 0.40 2.00 0.00 0.20 0.20 0.20 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Discontinued Product (PCN #02-06). Contact Rochester Electronics for Availability. www.latticesemi.com/sales/discontinueddevicessales.cfm LVCMOS25_12mA_out tEN, tDIS, tBUF LVCMOS25_16mA_out tEN, tDIS, tBUF LVCMOS33_4A_out LVCMOS33_5mA_out LVCMOS33_8mA_out tEN, tDIS, tBUF tEN, tDIS, tBUF tEN, tDIS, tBUF LVCMOS33_12mA_out tEN, tDIS, tBUF LVCMOS33_16mA_out tEN, tDIS, tBUF LVCMOS33_20mA_out tEN, tDIS, tBUF PCI_out AGP_1X_out SSTL3_I_out SSTL3_II_out SSTL2_I_out SSTL2_II_out CTT33_out CTT_25_out HSTL_I_out HSTL_III_out GTL+_out tIOI Input Adders CLK0 CLK1 CLK2 CLK3 tGCLK_IN tGCLK_IN tGCLK_IN tGCLK_IN tEN, tDIS, tBUF tEN, tDIS, tBUF tEN, tDIS, tBUF tEN, tDIS, tBUF tEN, tDIS, tBUF tEN, tDIS, tBUF tEN, tDIS, tBUF tEN, tDIS, tBUF tEN, tDIS, tBUF tEN, tDIS, tBUF tEN, tDIS, tBUF Note: Open drain timing is the same as corresponding LVCMOS timing. Timing v.1.3 27 Lattice Semiconductor ispMACH 5000B Family Data Sheet ispMACH 5256B Timing Adders (Cont). -4 Adder Type 1 2 3 4 5 6 7 tROUTE tROUTE tROUTE tROUTE tROUTE tROUTE tROUTE Base Parameter tBLA Additional Block Loading Adders 0.10 0.20 0.30 0.40 0.60 0.60 0.60 0.10 0.20 0.30 0.40 0.60 0.60 0.60 0.10 0.20 0.30 0.40 0.60 0.60 0.60 0.10 0.20 0.30 0.40 0.60 0.60 0.60 ns ns ns ns ns ns ns -5 -75 -10 Min. Max. Min. Max. Min. Max. Min. Max. Units Discontinued Product (PCN #02-06). Contact Rochester Electronics for Availability. www.latticesemi.com/sales/discontinueddevicessales.cfm Note: Open drain timing is the same as corresponding LVCMOS timing. Timing v.1.3 28 Lattice Semiconductor ispMACH 5000B Family Data Sheet Discontinued Product (PCN #02-06). Contact Rochester Electronics for Availability. www.latticesemi.com/sales/discontinueddevicessales.cfm ispMACH 5384B Timing Adders Adder Type tLP tIOI Input Adders LVCMOS18_in LVCMOS25_in LVCMOS33_in PCI_in AGP_1X_in SSTL3_I_in SSTL3_II_in SSTL2_I_in SSTL2_II_in CTT33_in CTT25_in HSTL_I_in HSTL_III_in GTL+_in LVDS_in LVPECL_D_in tIDO Output Adders Slow Slew LVCMOS18_4mA_out LVCMOS18_5mA_out LVCMOS18_8mA_out tEN, tBUF tEN, tDIS, tBUF tEN, tDIS, tBUF tEN, tDIS, tBUF Output configured for slow slew rate Output configured as 1.8V & 4mA Buffer Output configured as 1.8V & 5.33mA Buffer Output configured as 1.8V & 8mA Buffer Output configured as 1.8V & 12mA Buffer Output configured as 2.5V & 4mA Buffer Output configured as 2.5V & 5.33mA Buffer 1.50 0.80 0.50 0.10 -0.10 0.50 0.20 1.50 0.80 0.50 0.10 -0.10 0.50 0.20 1.50 0.80 0.50 0.10 -0.10 0.50 0.20 1.50 0.80 0.50 0.10 -0.10 0.50 0.20 ns ns ns ns ns ns tIN, tGCLK_IN, tRST, tGOE tIN, tGCLK_IN, tRST, tGOE tIN, tGCLK_IN, tRST, tGOE tIN, tGCLK_IN, tRST, tGOE tIN, tGCLK_IN, tRST, tGOE tIN, tGCLK_IN, tRST, tGOE tIN, tGCLK_IN, tRST, tGOE tIN, tGCLK_IN, tRST, tGOE tIN, tGCLK_IN, tRST, tGOE tIN, tGCLK_IN, tRST, tGOE tIN, tGCLK_IN, tRST, tGOE tIN, tGCLK_IN, tRST, tGOE tIN, tGCLK_IN, tRST, tGOE tIN, tGCLK_IN, tRST, tGOE tGCLK_IN tGCLK_IN Using LVCMOS1.8 standard Using LVCMOS2.5 standard Using LVCMOS3.3 standard Using PCI standard Using AGP-1X standard Using SSTL3_I standard Using SSTL3_II standard Using SSTL2_I standard Using SSTL2_II standard Using CTT3.3 standard Using CTT2.5 standard Using HSTL_I standard Using HSTL_III standard Using GTL+ standard Using LVDS standard Using LVDS differential standard 0.40 0.00 0.20 1.00 1.00 0.90 0.90 0.90 0.90 0.90 0.90 1.00 1.00 1.00 0.70 1.20 0.40 0.00 0.20 1.00 1.00 0.90 0.90 0.90 0.90 0.90 0.90 1.00 1.00 1.00 0.70 1.20 0.40 0.00 0.20 1.00 1.00 0.90 0.90 0.90 0.90 0.90 0.90 1.00 1.00 1.00 0.70 1.20 0.40 0.00 0.20 1.00 1.00 0.90 0.90 0.90 0.90 0.90 0.90 1.00 1.00 1.00 0.70 1.20 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Base Parameter tROUTE -4 Description Low Power Adder 1.00 -5 1.00 -75 1.00 -10 1.00 ns Min. Max. Min. Max. Min. Max. Min. Max. Units LVCMOS18_12mA_out tEN, tDIS, tBUF LVCMOS25_4mA_out LVCMOS25_5mA_out tEN, tDIS, tBUF tEN, tDIS, tBUF Note: Open drain timing is the same as corresponding LVCMOS timing. Timing v.1.0 29 Lattice Semiconductor ispMACH 5000B Family Data Sheet ispMACH 5384B Timing Adders (Cont.) Adder Type LVCMOS25_8mA_out Base Parameter tEN, tDIS, tBUF -4 Description Output configured as 2.5V & 8mA Buffer Output configured as 2.5V & 12mA Buffer Output configured as 2.5V & 16mA Buffer Output configured as 3.3V & 4mA Buffer Output configured as 3.3V & 5.33mA Buffer Output configured as 3.3V & 8mA Buffer Output configured as 3.3V & 12mA Buffer Output configured as 3.3V & 16mA Buffer Output configured as 3.3V & 20mA Buffer Using PCI standard Using AGP-1X standard Using SSTL3_I standard Using SSTL3_II standard Using SSTL2_I standard Using SSTL2_II standard Using CCT3.3 standard Using CCT2.5 standard Using HSTL_I standard Using HSTL_III standard Using GTL+ standard -5 -75 -10 Min. Max. Min. Max. Min. Max. Min. Max. Units 0.00 -0.10 -0.20 0.80 0.20 0.00 -0.10 -0.10 -0.20 -0.20 -0.20 0.50 0.10 0.50 -0.10 0.80 0.20 0.10 0.40 2.00 0.00 0.20 0.20 0.20 0.00 -0.10 -0.20 0.80 0.20 0.00 -0.10 -0.10 -0.20 -0.20 -0.20 0.50 0.10 0.50 -0.10 0.80 0.20 0.10 0.40 2.00 0.00 0.20 0.20 0.20 0.00 -0.10 -0.20 0.80 0.20 0.00 -0.10 -0.10 -0.20 -0.20 -0.20 0.50 0.10 0.50 -0.10 0.80 0.20 0.10 0.40 2.00 0.00 0.20 0.20 0.20 0.00 -0.10 -0.20 0.80 0.20 0.00 -0.10 -0.10 -0.20 -0.20 -0.20 0.50 0.10 0.50 -0.10 0.80 0.20 0.10 0.40 2.00 0.00 0.20 0.20 0.20 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Discontinued Product (PCN #02-06). Contact Rochester Electronics for Availability. www.latticesemi.com/sales/discontinueddevicessales.cfm LVCMOS25_12mA_out tEN, tDIS, tBUF LVCMOS25_16mA_out tEN, tDIS, tBUF LVCMOS33_4mA_out LVCMOS33_5mA_out LVCMOS33_8mA_out tEN, tDIS, tBUF tEN, tDIS, tBUF tEN, tDIS, tBUF LVCMOS33_12mA_out tEN, tDIS, tBUF LVCMOS33_16mA_out tEN, tDIS, tBUF LVCMOS33_20mA_out tEN, tDIS, tBUF PCI_out AGP_1X_out SSTL3_I_out SSTL3_II_out SSTL2_I_out SSTL2_II_out CTT33_out CTT_25_out HSTL_I_out HSTL_III_out GTL+_out tIOI Input Adders CLK0 CLK1 CLK2 CLK3 tGCLK_IN tGCLK_IN tGCLK_IN tGCLK_IN tEN, tDIS, tBUF tEN, tDIS, tBUF tEN, tDIS, tBUF tEN, tDIS, tBUF tEN, tDIS, tBUF tEN, tDIS, tBUF tEN, tDIS, tBUF tEN, tDIS, tBUF tEN, tDIS, tBUF tEN, tDIS, tBUF tEN, tDIS, tBUF Note: Open drain timing is the same as corresponding LVCMOS timing. Timing v.1.0 30 Lattice Semiconductor ispMACH 5000B Family Data Sheet ispMACH 5384B Timing Adders (Cont.) -4 Adder Type 1 2 3 4 5 6 7 8 9 10 11 tROUTE tROUTE tROUTE tROUTE tROUTE tROUTE tROUTE tROUTE tROUTE tROUTE tROUTE Base Parameter tBLA Additional Block Loading Adders 0.20 0.40 0.60 0.80 1.00 1.10 1.20 1.20 1.20 1.20 1.20 0.20 0.40 0.60 0.80 1.00 1.10 1.20 1.20 1.20 1.20 1.20 0.20 0.40 0.60 0.80 1.00 1.10 1.20 1.20 1.20 1.20 1.20 0.20 0.40 0.60 0.80 1.00 1.10 1.20 1.20 1.20 1.20 1.20 ns ns ns ns ns ns ns ns ns ns ns -5 -75 -10 Min. Max. Min. Max. Min. Max. Min. Max. Units Discontinued Product (PCN #02-06). Contact Rochester Electronics for Availability. www.latticesemi.com/sales/discontinueddevicessales.cfm Note: Open drain timing is the same as corresponding LVCMOS timing. Timing v.1.0 31 Lattice Semiconductor ispMACH 5000B Family Data Sheet Discontinued Product (PCN #02-06). Contact Rochester Electronics for Availability. www.latticesemi.com/sales/discontinueddevicessales.cfm ispMACH 5512B Timing Adders Adder Type tLP tIOI Input Adders LVCMOS18_in LVCMOS25_in LVCMOS33_in PCI_in AGP_1X_in SSTL3_I_in SSTL3_II_in SSTL2_I_in SSTL2_II_in CTT33_in CTT25_in HSTL_I_in HSTL_III_in GTL+_in LVDS_in LVPECL_D_in tIOO Output Adders Slow Slew LVCMOS18_4mA_out LVCMOS18_5mA_out LVCMOS18_8mA_out tEN, tBUF tEN, tDIS, tBUF tEN, tDIS, tBUF tEN, tDIS, tBUF Output configured for slow slew rate Output configured as 1.8V & 4mA Buffer Output configured as 1.8V & 5.33mA Buffer Output configured as 1.8V & 8mA Buffer Output configured as 1.8V & 12mA Buffer Output configured as 2.5V & 4mA Buffer Output configured as 2.5V & 5.33mA Buffer 1.50 0.80 0.50 0.10 -0.10 0.50 0.20 1.50 0.80 0.50 0.10 -0.10 0.50 0.20 1.50 0.80 0.50 0.10 -0.10 0.50 0.20 1.50 0.80 0.50 0.10 -0.10 0.50 0.20 ns ns ns ns ns ns ns tIN, tGCLK_IN, tRST, tGOE tIN, tGCLK_IN, tRST, tGOE tIN, tGCLK_IN, tRST, tGOE tIN, tGCLK_IN, tRST, tGOE tIN, tGCLK_IN, tRST, tGOE tIN, tGCLK_IN, tRST, tGOE tIN, tGCLK_IN, tRST, tGOE tIN, tGCLK_IN, tRST, tGOE tIN, tGCLK_IN, tRST, tGOE tIN, tGCLK_IN, tRST, tGOE tIN, tGCLK_IN, tRST, tGOE tIN, tGCLK_IN, tRST, tGOE tIN, tGCLK_IN, tRST, tGOE tIN, tGCLK_IN, tRST, tGOE tGCLK_IN tGCLK_IN Using LVCMOS1.8 standard Using LVCMOS2.5 standard Using LVCMOS3.3 standard Using PCI standard Using AGP-1X standard Using SSTL3_I standard Using SSTL3_II standard Using SSTL2_I standard Using SSTL2_II standard Using CTT3.3 standard Using CTT2.5 standard Using HSTL_I standard Using HSTL_III standard Using GTL+ standard Using LVDS standard Using LVDS differential standard 0.30 0.00 0.20 1.00 1.00 0.90 0.90 0.90 0.90 0.90 0.90 1.00 1.00 1.00 1.00 1.50 0.30 0.00 0.20 1.00 1.00 0.90 0.90 0.90 0.90 0.90 0.90 1.00 1.00 1.00 1.00 1.50 0.30 0.00 0.20 1.00 1.00 0.90 0.90 0.90 0.90 0.90 0.90 1.00 1.00 1.00 1.00 1.50 0.30 0.00 0.20 1.00 1.00 0.90 0.90 0.90 0.90 0.90 0.90 1.00 1.00 1.00 1.00 1.50 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Base Parameter tROUTE -45 Description Low Power Adder 1.00 -75 1.00 -10 1.00 -12 1.00 ns Min. Max. Min. Max. Min. Max. Min. Max. Units LVCMOS18_12mA_out tEN, tDIS, tBUF LVCMOS25_4mA_out LVCMOS25_5mA_out tEN, tDIS, tBUF tEN, tDIS, tBUF Note: Open drain timing is the same as corresponding LVCMOS timing. Timing v.1.1 32 Lattice Semiconductor ispMACH 5000B Family Data Sheet ispMACH 5512B Timing Adders (Cont.) Adder Type LVCMOS25_8mA_out Base Parameter tEN, tDIS, tBUF -45 Description Output configured as 2.5V & 8mA Buffer Output configured as 2.5V & 12mA Buffer Output configured as 2.5V & 16mA Buffer Output configured as 3.3V & 4mA Buffer Output configured as 3.3V & 5.33mA Buffer Output configured as 3.3V & 8mA Buffer Output configured as 3.3V & 12mA Buffer Output configured as 3.3V & 16mA Buffer Output configured as 3.3V & 20mA Buffer Using PCI standard Using AGP-1X standard Using SSTL3_I standard Using SSTL3_II standard Using SSTL2_I standard Using SSTL2_II standard Using CCT3.3 standard Using CCT2.5 standard Using HSTL_I standard Using HSTL_III standard Using GTL+ standard -75 -10 -12 Min. Max. Min. Max. Min. Max. Min. Max. Units 0.00 -0.10 -0.20 0.80 0.20 0.00 -0.10 -0.10 -0.20 -0.20 -0.20 0.50 0.10 0.50 -0.10 0.80 0.20 0.10 0.50 2.00 0.00 -0.10 -0.20 0.80 0.20 0.00 -0.10 -0.10 -0.20 -0.20 -0.20 0.50 0.10 0.50 -0.10 0.80 0.20 0.10 0.50 2.00 0.00 -0.10 -0.20 0.80 0.20 0.00 -0.10 -0.10 -0.20 -0.20 -0.20 0.50 0.10 0.50 -0.10 0.80 0.20 0.10 0.50 2.00 0.00 -0.10 -0.20 0.80 0.20 0.00 -0.10 -0.10 -0.20 -0.20 -0.20 0.50 0.10 0.50 -0.10 0.80 0.20 0.10 0.50 2.00 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Discontinued Product (PCN #02-06). Contact Rochester Electronics for Availability. www.latticesemi.com/sales/discontinueddevicessales.cfm LVCMOS25_12mA_out tEN, tDIS, tBUF LVCMOS25_16mA_out tEN, tDIS, tBUF LVCMOS33_4mA_out LVCMOS33_5mA_out LVCMOS33_8mA_out tEN, tDIS, tBUF tEN, tDIS, tBUF tEN, tDIS, tBUF LVCMOS33_12mA_out tEN, tDIS, tBUF LVCMOS33_16mA_out tEN, tDIS, tBUF LVCMOS33_20mA_out tEN, tDIS, tBUF PCI_out AGP_1X_out SSTL3_I_out SSTL3_II_out SSTL2_I_out SSTL2_II_out CTT33_out CTT_25_out HSTL_I_out HSTL_III_out GTL+_out tEN, tDIS, tBUF tEN, tDIS, tBUF tEN, tDIS, tBUF tEN, tDIS, tBUF tEN, tDIS, tBUF tEN, tDIS, tBUF tEN, tDIS, tBUF tEN, tDIS, tBUF tEN, tDIS, tBUF tEN, tDIS, tBUF tEN, tDIS, tBUF Note: Open drain timing is the same as corresponding LVCMOS timing. Timing v.1.1 33 Lattice Semiconductor ispMACH 5000B Family Data Sheet ispMACH 5512B Timing Adders (Cont.) Adder Type tIOI Input Adders CLK0 CLK1 CLK2 CLK3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 tGCLK_IN tGCLK_IN tGCLK_IN tGCLK_IN tROUTE tROUTE tROUTE tROUTE tROUTE tROUTE tROUTE tROUTE tROUTE tROUTE tROUTE tROUTE tROUTE tROUTE tROUTE 0.00 0.20 0.20 0.20 0.30 0.70 0.90 1.10 1.20 1.30 1.50 1.60 1.80 1.90 2.10 2.40 2.60 2.90 3.00 0.00 0.20 0.20 0.20 0.30 0.70 0.90 1.10 1.20 1.30 1.50 1.60 1.80 1.90 2.10 2.40 2.60 2.90 3.00 0.00 0.20 0.20 0.20 0.30 0.70 0.90 1.10 1.20 1.30 1.50 1.60 1.80 1.90 2.10 2.40 2.60 2.90 3.00 0.00 0.20 0.20 0.20 0.30 0.70 0.90 1.10 1.20 1.30 1.50 1.60 1.80 1.90 2.10 2.40 2.60 2.90 3.00 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns -45 Base Parameter -75 -10 -12 Min. Max. Min. Max. Min. Max. Min. Max. Units Discontinued Product (PCN #02-06). Contact Rochester Electronics for Availability. www.latticesemi.com/sales/discontinueddevicessales.cfm tBLA Additional Block Loading Adders Note: Open drain timing is the same as corresponding LVCMOS timing. Timing v.1.1 Boundary Scan Timing Specifications Symbol tBTCP tBTCH tBTCL tBTSU tBTH tBRF tBTCO tBTOZ tBTVO tBVTCPSU tBTCPH tBTUCO tBTUOZ tBTUOV Parameter TCK [BSCAN test] clock pulse width TCK [BSCAN test] pulse width high TCK [BSCAN test] pulse width low TCK [BSCAN test] setup time TCK [BSCAN test] hold time TCK [BSCAN test] rise and fall time TAP controller falling edge of clock to valid output TAP controller falling edge of clock to data output disable TAP controller falling edge of clock to data output enable BSCAN test Capture register setup time BSCAN test Capture register hold time BSCAN test Update reg, falling edge of clock to valid output BSCAN test Update reg, falling edge of clock to output disable BSCAN test Update reg, falling edge of clock to output enable Min. 125 62.5 62.5 25 25 50 -- -- -- 25 25 -- -- -- Max. -- -- -- -- -- -- 25 25 25 -- -- 50 50 50 Units ns ns ns ns ns mV/ns ns ns ns ns ns ns ns ns 34 Lattice Semiconductor ispMACH 5000B Family Data Sheet Power Consumption ispMACH 5000B Typical ICC vs. Frequency 600 500 400 Discontinued Product (PCN #02-06). Contact Rochester Electronics for Availability. www.latticesemi.com/sales/discontinueddevicessales.cfm ispMACH 5512B (High Power Mode) ispMACH 5384B (High Power Mode) ispMACH 5512B (Low Power Mode) ispMACH 5384B (Low Power Mode) ispMACH 5256B (High Power Mode) ICC (mA) 300 200 100 0 0 50 100 150 200 ispMACH 5256B (Low Power Mode) ispMACH 5128B (High Power Mode) ispMACH 5128B (Low Power Mode) 250 300 fMAX (MHz) Note: The devices are configured with maximum number of 16-bit counters, typical current at 2.5V, 25C. Power Estimation Coefficients Device ispMACH 5128B ispMACH 5256B ispMACH 5384B ispMACH 5512B K0 0.0055 0.0055 0.0055 0.0055 K1 0.0055 0.0055 0.0055 0.0055 K2 0.005 0.005 0.0065 0.008 K3 0.273 0.2215 0.2215 0.2215 K4 0.091 0.075 0.075 0.075 IDC (mA) 10.6 10.5 18.4 22.9 IDCO (mA) 1.2 1.2 1.2 1.2 Note: For further information about the use of these coefficients, refer to Lattice technical note number TN1023, Power Estimation in ispMACH 5000B Devices. The device power, IDEVICE, is calculated from the following equation: IDEVICE = IDEVICE-AC + IDEVICE-DC Each term in IDEVICE is further defined as: IDEVICE-AC = FAVE [(K0 * PTHP) + (K1 * PTLP) + K2 * GRPLINES)] IDEVICE-DC = K3 * PTHP + K4 * PTLP + IDC + IDCO where: PTHP = Number of product terms in high power PTLP = Number of product terms in low power FAVE = Average output frequency of switching product terms in MHz K0 = average current per product term in high power/MHz K1 = average current per product term in low power/MHz K2 = average current per GRP line/MHz K3 = DC current per product term in high power K4 = DC current per product term in low power IDC = Static Device Current IDCO = Static I/O Bank Current ICC estimates are based on typical conditions (VCC = 2.5V, 25C). These values are for estimates only. Since the value of ICC is sensitive to operating conditions and the program in the device, the actual ICC should be verified. 35 Lattice Semiconductor ispMACH 5000B Family Data Sheet Switching Test Conditions Figure 9 shows the output test load that is used for AC testing. The specific values for resistance, capacitance, voltage, and other test conditions are shown in Table 3. Figure 9. Output Test Load, LVTTL and LVCMOS Standards VCCO R1 DUT R2 CL* Test Point Discontinued Product (PCN #02-06). Contact Rochester Electronics for Availability. www.latticesemi.com/sales/discontinueddevicessales.cfm *CL includes Test Fixture and Probe Capacitance. 0213A/ispm5kb Table 3. Test Fixture Required Components Test Condition Default LVCMOS 2.5 I/O (L -> H, H -> L) Other LVCMOS Settings (L -> H, H -> L) Default LVCMOS 2.5 I/O (Z -> H) Default LVCMOS 2.5 I/O (Z -> L) Default LVCMOS 2.5 I/O (H -> Z) Default LVCMOS 2.5 I/O (L -> Z) R1 188 188 188 R2 188 188 188 CL 35pF 35pF 35pF 35pF 5pF 5pF Timing Ref. VCCO/2 LVCMOS 3.3 = 1.5V LVCMOS 2.5 = VCCO/2 LVCMOS 1.8 = VCCO/2 VCCO/2 VCCO/2 VOH - 0.15 VOL + 0.15 2.3V LVCMOS 3.3 = 3.0V LVCMOS 2.5 = 2.3V LVCMOS 1.8 = 1.65V 2.3V 2.3V 2.3V 2.3V VCCO Output test conditions for all other interfaces are determined by the respective standards. 36 Lattice Semiconductor ispMACH 5000B Family Data Sheet Signal Descriptions Signal Names TMS TCK TDI TDO TOE GOE0, GOE1 RESETB Description Input - This pin is the Test Mode Select input, which is used to control the IEEE 1149.1 state machine. Input - This pin is the Test Clock input pin, used to clock the IEEE 1149.1 state machine. Input - This pin is the IEEE 1149.1 Test Data In pin, used to load data. Output - This pin is the IEEE 1149.1 Test Data Out pin used to shift data out. Input - Test Output Enable pin. TOE tristates all I/O pins when a logic low is driven. Input - These two pins are the Global Output Enable input pins. Dedicated Reset Input - This pin resets all registers in the devices. The global polarity (active high or low input) for this pin is selectable. Input/Output - These are the general purpose I/O used by the logic array. y is the GLB reference (alpha) and z is the macrocell reference (numeric). z: 0-31 ispMACH 5128B yzz ispMACH 5256B ispMACH 5384B ispMACH 5512B GND NC VCC GCLK0, GCLK1, GCLK2, GCLK3 VREF0, VREF1, VREF2, VREF3 VCCO0, VCCO1, VCCO2, VCCO3 Ground No connect Vcc - These are the power supply pins for the logic core. Inputs - These pins are dedicated CLK inputs. Inputs - These are the reference supplies for the I/O banks. VCC - These are the VCC supplies for each I/O bank. y: A-D, z: 0-31 y: A-H, z: 0-31 y: A-L, z: 0-31 y: A-P, z: 0-31 Discontinued Product (PCN #02-06). Contact Rochester Electronics for Availability. www.latticesemi.com/sales/discontinueddevicessales.cfm 37 Lattice Semiconductor ispMACH 5000B Family Data Sheet ispMACH 5000B Power Supply and NC Connections Signal VCC 128-Pin TQFP1,2 13, 45, 77, 109 208-Pin PQFP1,2 11, 48, 74, 115, 152, 178 5256B: 18, 189, 203 5384B/5512B: 7, 18, 189, 203 VCCO1 VCCO2 28, 41 56, 69 41, 56, 70 5256B: 85, 99, 122 5384B/5512B: 85, 99, 109, 122 VCCO3 VREF0 VREF1 VREF2 VREF3 GND 92, 105 124 37 61 100 145, 160, 174 193 66 90 169 C10, C14, G14 E7 M7 R13 A8 A1, C5, C12, E3, E14, G7, G8, G9, G10, H8, H9, H10, J7, J8, J9, K7, K8, K9, K10, M3, M14, P5, P12 B18, D16, E14, E17, E21, F18, G19, J18 A9 AA10 AA13 A15 A1, A22, C3, C20, D4, D19, E7, E16, G5, G7, G8, G9, G10, G11, G12, G13, G14, G15, G16, G18, H7, H8, H9, H10, H11, H12, H13, H14, H15, H16, J7, J8, J9, J10, J11, J12, J13, J14, J15, J16, K7, K8, K9, K10, K11, K12, K13, K14, K15, K16, L8, L9, L10, L11, L12, L13, L14, L15, M7, M8, M9, M10, M11, M12, M13, M14, M15, M16, N7, N8, N9, N10, N11, N12, N13, N14, N15, N16, P7, P8, P9, P10, P11, P12, P13, P14, P15, P16, R7, R8, R9, R10, R11, R12, R13, R14, R15, R16, T4, T7, T8, T9, T10, T11, T12, T13, T14, T15, T16, T19, W7, W16, AB1, AB22 5512B: A6, A7, A8, A19, A20, A21, B7, B8, B19, B20, B22, C7, C8, C10, C16, C17, D9, D15, D18, E3, E10, F1, F3, F4, F9, F10, F16, F17, F19, F20, G1, G2, G3, G6, G17, G20, G21, G22, H1, H2, H5, H6, H17, H18, H19, H20, H21, H22, L6, L7, L16, N18, P4, AA1 K3, P3, P7 K14, P10, P14 P5, U5, V6, V9, Y3, P18, U18, V14, V17, Y20, 256-Ball fpBGA3 484-Ball fpBGA3 F8, F9, H6, H11, J6, J11, L8, B2, B6, B17, B21, C9, C14, E5, E18, L9 F2, F21, J3, J20, P3, P20, U2, U21, Y9, Y14, AA2, AA6, AA17, AA21 C3, C7, G3 B5, D7, E2, E6, E9, F5, G4, J5 Discontinued Product (PCN #02-06). Contact Rochester Electronics for Availability. www.latticesemi.com/sales/discontinueddevicessales.cfm VCCO0 5, 120 6, 20, 27, 40, 52, 5256B: 19, 20, 39, 40, 57, 70, 84, 91, 55, 69, 81, 86, 100, 104, 116, 121 123, 124, 143, 144, 159, 173, 185, 190, 204 5384B/5512B: 8, 19, 20, 39, 40, 55, 69, 81, 86, 100, 110, 123, 124, 143, 144, 159, 173, 185, 190, 204 NC4 5128B: 45, 52, 109, 116 5256B: 1, 2, 7, 8, 101, 102, 103, 104, 105, 106, 109, 110, 205, 206, 207, 208 5256B: A11, A12, A13, A14, B1, B2, B11, B12, B13, B16, C1, C2, C13, C15, C16, D14, D15, D16, E13, E15, F6, F7, F10, F11, G6, G11, H1, H7, H16, J1, J10, K6, K11, L5, L6, L7, L10, L11, M4, N2, N3, N4, N5, P1, P2, P4, P6, P15, P16, R4, R5, R6, R15, R16, T4, T5, T6 5384B: A11, A12, A13, B13, C13, H1, H7, H16, J1, J10, P6, R5, R6, T5, T6 5512B: H1, H7, H16, J1, J10 1. All grounds must be electrically connected at the board level. 2. Not all grounds internally connected within the device. Pin orientation follows the conventional order from pin 1 marking of the top side view and counter-clockwise. 3. Balls for ground (GND), VCC and VCCO signals are connected within the substrate. Pin orientation A1 starts from the upper left corner of the top side view with alphabetical order ascending vertically and numerical order ascending horizontally. 4. No connects should not be connected to any active signals, VCC, VCCO, or GND. 38 Lattice Semiconductor ispMACH 5000B Family Data Sheet Discontinued Product (PCN #02-06). Contact Rochester Electronics for Availability. www.latticesemi.com/sales/discontinueddevicessales.cfm ispMACH 5128B, 5256B Logic Signal Connections: 128 TQFP Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 Bank Number 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ispMACH 5128B GLB/MC/Pad D12 D10 D9 D8 VCCO (Bank 0) GND (Bank 0) D6 D5 D4 D2 D1 D0 VCC GCLK0 GCLK1 TDI TMS TCK TDO GND A0 A1 A2 A4 A5 A6 GND (Bank 1) VCCO (Bank 1) A8 A9 A10 A12 A14 A16 A17 A18 A20/VREF1 A21 A22 GND (Bank 1) VCCO (Bank 1) ispMACH 5256B GLB/MC/Pad H16 H14 H12 H10 VCCO (Bank 0) GND (Bank 0) H8 H6 H5 H4 H2 H0 VCC GCLK0 GCLK1 TDI TMS TCK TDO GND A0 A2 A4 A5 A6 A8 GND (Bank 1) VCCO (Bank 1) A10 A12 A14 A16 A20 B10 B12 B14 B16/VREF1 B18 B20 GND (Bank 1) VCCO (Bank 1) 39 Lattice Semiconductor ispMACH 5000B Family Data Sheet ispMACH 5128B, 5256B Logic Signal Connections: 128 TQFP (Cont.) Pin Number 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 Bank Number 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 ispMACH 5128B GLB/MC/Pad A24 A25 A26 NC A28 A29 A30 B0 B1 B2 NC B4 B5 B6 VCCO (Bank 2) GND (Bank 2) B8 B9 B10 B12/VREF2 B13 B14 B16 B18 B20 B21 B22 VCCO (Bank 2) GND (Bank 2) B24 B25 B26 B28 B29 B30 VCC TOE RESETB GOE0 GOE1 GCLK2 GCLK3 GND ispMACH 5256B GLB/MC/Pad B21 B22 B24 VCC B26 B28 B30 C0 C2 C4 GND C5 C6 C8 VCCO (Bank 2) GND (Bank 2) C10 C12 C14 C16/VREF2 C18 C20 D10 D14 D16 D18 D20 VCCO (Bank 2) GND (Bank 2) D21 D22 D24 D26 D28 D30 VCC TOE RESETB GOE0 GOE1 GCLK2 GCLK3 GND Discontinued Product (PCN #02-06). Contact Rochester Electronics for Availability. www.latticesemi.com/sales/discontinueddevicessales.cfm 40 Lattice Semiconductor ispMACH 5000B Family Data Sheet ispMACH 5128B, 5256B Logic Signal Connections: 128 TQFP (Cont.) Pin Number 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 Bank Number 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 0 0 0 0 0 0 0 0 0 0 0 0 0 ispMACH 5128B GLB/MC/Pad C30 C29 C28 C26 C25 C24 GND (Bank 3) VCCO (Bank 3) C22 C21 C20 C18 C16 C14 C13 C12/VREF3 C10 C9 C8 GND (Bank 3) VCCO (Bank 3) C6 C5 C4 NC C2 C1 C0 D30 D29 D28 NC D26 D25 D24 VCCO (Bank 0) GND (Bank 0) D22 D21 D20/VREF0 D18 D17 ispMACH 5256B GLB/MC/Pad E30 E28 E26 E24 E22 E21 GND (Bank 3) VCCO (Bank 3) E20 E18 E16 E14 E10 F20 F18 F16/VREF3 F14 F12 F10 GND (Bank 3) VCCO (Bank 3) F8 F6 F5 VCC F4 F2 F0 G30 G28 G26 GND G24 G22 G21 VCCO (Bank 0) GND (Bank 0) G20 G18 G16/VREF0 G14 G12 Discontinued Product (PCN #02-06). Contact Rochester Electronics for Availability. www.latticesemi.com/sales/discontinueddevicessales.cfm 41 Lattice Semiconductor ispMACH 5000B Family Data Sheet ispMACH 5128B, 5256B Logic Signal Connections: 128 TQFP (Cont.) Pin Number 127 128 Bank Number 0 0 ispMACH 5128B GLB/MC/Pad D16 D14 ispMACH 5256B GLB/MC/Pad G10 H20 Discontinued Product (PCN #02-06). Contact Rochester Electronics for Availability. www.latticesemi.com/sales/discontinueddevicessales.cfm ispMACH 5256B, 5384B, 5512B Logic Signal Connections: 208 PQFP Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Bank Number 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ispMACH 5256B GLB/MC/Pad NC NC H30 H28 H26 H24 NC NC H22 H21 VCC H20 H18 H16 H14 H12 H10 VCC (Bank 0) GND GND (Bank 0) H8 H6 H5 H4 H2 H0 GCLK0 GCLK1 TDI TMS TCK TDO ispMACH 5384B GLB/MC/Pad K14 K12 K10 K8 K6 K4 VCCO (Bank 0) GND (Bank 0) K2 K0 VCC L22 L20 L18 L16 L14 L12 VCCO (Bank 0) GND GND (Bank 0) L10 L8 L6 L4 L2 L0 GCLK0 GCLK1 TDI TMS TCK TDO ispMACH 5512B GLB/MC/Pad O30 O28 O26 O24 O22 O20 VCCO (Bank 0) GND (Bank 0) O18 O16 VCC P22 P20 P18 P16 P14 P12 VCCO (Bank 0) GND GND (Bank 0) P10 P8 P6 P4 P2 P0 GCLK0 GCLK1 TDI TMS TCK TDO 42 Lattice Semiconductor ispMACH 5000B Family Data Sheet ispMACH 5256B, 5384B, 5512B Logic Signal Connections: 208 PQFP (Cont.) Pin Number 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 Bank Number 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ispMACH 5256B GLB/MC/Pad A0 A2 A4 A5 A6 A8 GND (Bank 1) GND VCCO (Bank 1) A10 A12 A14 A16 A18 A20 VCC A21 A22 A24 A26 A28 A30 GND (Bank 1) VCCO (Bank 1) B0 B2 B4 B5 B6 B8 B10 B12 B14 B16/VREF1 B18 B20 GND (Bank 1) VCCO (Bank 1) ispMACH 5384B GLB/MC/Pad A0 A2 A4 A6 A8 A10 GND (Bank 1) GND VCCO (Bank 1) A12 A14 A16 A18 A20 A22 VCC B12 B14 B16 B18 B20 B21 GND (Bank 1) VCCO (Bank 1) C0 C2 C4 C5 C6 C8 C10 C12 C14 C16/VREF1 C18 C20 GND (Bank 1) VCCO (Bank 1) ispMACH 5512B GLB/MC/Pad A0 A2 A4 A6 A8 A10 GND (Bank 1) GND VCCO (Bank 1) A12 A14 A16 A18 A20 A22 VCC B12 B14 B16 B18 B20 B21 GND (Bank 1) VCCO (Bank 1) C20 C24 C26 C28 D0 D2 D4 D6 D8 D10/VREF1 D12 D16 GND (Bank 1) VCCO (Bank 1) Discontinued Product (PCN #02-06). Contact Rochester Electronics for Availability. www.latticesemi.com/sales/discontinueddevicessales.cfm 43 Lattice Semiconductor ispMACH 5000B Family Data Sheet ispMACH 5256B, 5384B, 5512B Logic Signal Connections: 208 PQFP (Cont.) Pin Number 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 Bank Number 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 ispMACH 5256B GLB/MC/Pad B21 B22 B24 VCC B26 B28 B30 C0 C2 C4 GND C5 C6 C8 VCCO (Bank 2) GND (Bank 2) C10 C12 C14 C16/VREF2 C18 C20 C21 C22 C24 C26 C28 C30 VCCO (Bank 2) GND (Bank 2) NC NC NC NC NC NC D0 D2 NC ispMACH 5384B GLB/MC/Pad C21 C22 C24 VCC C26 C28 C30 D0 D2 D4 GND D5 D6 D8 VCCO (Bank 2) GND (Bank 2) D10 D12 D14 D16/VREF2 D18 D20 D21 D22 D24 D26 D28 D30 VCCO (Bank 2) GND (Bank 2) E4 E6 E8 E10 E20 E22 E24 E26 VCCO (Bank 2) ispMACH 5512B GLB/MC/Pad D18 D20 D22 VCC D24 D26 D28 E0 E2 E4 GND E6 E8 E10 VCCO (Bank 2) GND (Bank 2) E12 E16 E18 E20/VREF2 E22 E24 E26 E28 F0 F2 F4 F6 VCCO (Bank 2) GND (Bank 2) G4 G6 G8 G10 G20 G22 G24 G26 VCCO (Bank 2) Discontinued Product (PCN #02-06). Contact Rochester Electronics for Availability. www.latticesemi.com/sales/discontinueddevicessales.cfm 44 Lattice Semiconductor ispMACH 5000B Family Data Sheet ispMACH 5256B, 5384B, 5512B Logic Signal Connections: 208 PQFP (Cont.) Pin Number 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 Bank Number 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 3 3 3 3 3 3 3 3 3 3 3 ispMACH 5256B GLB/MC/Pad NC D4 D5 D6 D8 VCC D10 D12 D14 D16 D18 D20 VCCO (Bank 2) GND GND (Bank 2) D21 D22 D24 D26 D28 D30 TOE RESETB GOE0 GOE1 GCLK2 GCLK3 E30 E28 E26 E24 E22 E21 GND (Bank 3) GND VCCO (Bank 3) E20 E18 E16 ispMACH 5384B GLB/MC/Pad GND (Bank 2) E28 E30 F0 F2 VCC F8 F10 F12 F14 F16 F18 VCCO (Bank 2) GND GND (Bank 2) F20 F22 F24 F26 F28 F30 TOE RESETB GOE0 GOE1 GCLK2 GCLK3 G30 G28 G26 G24 G22 G20 GND (Bank 3) GND VCCO (Bank 3) G18 G16 G14 ispMACH 5512B GLB/MC/Pad GND (Bank 2) G28 G30 H0 H2 VCC H8 H10 H12 H14 H16 H18 VCCO (Bank 2) GND GND (Bank 2) H20 H22 H24 H26 H28 H30 TOE RESETB GOE0 GOE1 GCLK2 GCLK3 I30 I28 I26 I24 I22 I20 GND (Bank 3) GND VCCO (Bank 3) I18 I16 I14 Discontinued Product (PCN #02-06). Contact Rochester Electronics for Availability. www.latticesemi.com/sales/discontinueddevicessales.cfm 45 Lattice Semiconductor ispMACH 5000B Family Data Sheet ispMACH 5256B, 5384B, 5512B Logic Signal Connections: 208 PQFP (Cont.) Pin Number 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 Bank Number 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 0 0 0 0 0 0 ispMACH 5256B GLB/MC/Pad E14 E12 E10 VCC E8 E6 E5 E4 E2 E0 GND (Bank 3) VCCO (Bank 3) F30 F28 F26 F24 F22 F21 F20 F18 F16/VREF3 F14 F12 F10 GND (Bank 3) VCCO (Bank 3) F8 F6 F5 VCC F4 F2 F0 G30 G28 G26 GND G24 G22 G21 ispMACH 5384B GLB/MC/Pad G12 G10 G8 VCC H18 H16 H14 H12 H10 H8 GND (Bank 3) VCCO (Bank 3) I30 I28 I26 I24 I22 I21 I20 I18 I16/VREF3 I14 I12 I10 GND (Bank 3) VCCO (Bank 3) I8 I6 I5 VCC I4 I2 I0 J30 J28 J26 GND J24 J22 J21 ispMACH 5512B GLB/MC/Pad I12 I10 I8 VCC J0 K30 K28 K26 K24 K22 GND (Bank 3) VCCO (Bank 3) L30 L28 L26 L24 L22 L21 L20 L18 L16/VREF3 L14 L12 L10 GND (Bank 3) VCCO (Bank 3) L8 L6 L5 VCC L4 L2 L0 M30 M28 M26 GND M24 M22 M21 Discontinued Product (PCN #02-06). Contact Rochester Electronics for Availability. www.latticesemi.com/sales/discontinueddevicessales.cfm 46 Lattice Semiconductor ispMACH 5000B Family Data Sheet ispMACH 5256B, 5384B, 5512B Logic Signal Connections: 208 PQFP (Cont.) Pin Number 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 Bank Number 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ispMACH 5256B GLB/MC/Pad VCCO (Bank 0) GND (Bank 0) G20 G18 G16/VREF0 G14 G12 G10 G8 G6 G5 G4 G2 G0 VCCO (Bank 0) GND (Bank 0) NC NC NC NC ispMACH 5384B GLB/MC/Pad VCCO (Bank 0) GND (Bank 0) J20 J18 J16/VREF0 J14 J12 J10 J8 J6 J5 J4 J2 J0 VCCO (Bank 0) GND (Bank 0) K26 K24 K22 K20 ispMACH 5512B GLB/MC/Pad VCCO (Bank 0) GND (Bank 0) M20 M18 M16/VREF0 M14 M12 M10 M8 M6 M5 M4 M2 M0 VCCO (Bank 0) GND (Bank 0) N8 N6 N5 N4 Discontinued Product (PCN #02-06). Contact Rochester Electronics for Availability. www.latticesemi.com/sales/discontinueddevicessales.cfm ispMACH 5256B, 5384B, 5512B Logic Signal Connections: 256 fpBGA Ball Number B2 B1 C2 C1 F7 F6 E5 D4 D3 D2 Bank Number 0 0 0 0 0 0 0 0 0 0 0 0 ispMACH 5256B GLB/MC/Pad VCCO (Bank 0) GND (Bank 0) VCC GND NC NC NC NC NC NC H30 H28 H26 H24 ispMACH 5384B GLB/MC/Pad VCCO (Bank 0) GND (Bank 0) VCC GND K26 K24 K22 K20 K14 K12 K10 K8 K6 K4 ispMACH 5512B GLB/MC/Pad VCCO (Bank 0) GND (Bank 0) VCC GND N8 N6 N5 N4 O30 O28 O26 O24 O22 O20 47 Lattice Semiconductor ispMACH 5000B Family Data Sheet ispMACH 5256B, 5384B, 5512B Logic Signal Connections: 256 fpBGA (Cont.) Ball Number D1 E4 G6 F5 E2 E1 F4 F3 F2 G5 G4 F1 G2 G1 H5 H1 H7 H4 J4 H3 H2 J3 J1 J2 K1 K2 L1 J5 L2 K4 Bank Number 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 ispMACH 5256B GLB/MC/Pad NC NC H22 H21 NC H20 H18 H16 H14 H12 H10 GND VCC VCCO (Bank 0) GND (Bank 0) H8 H6 H5 H4 H2 H0 NC NC GCLK0 GCLK1 TDI TMS TCK NC TDO VCC GND VCC GND A0 A2 A4 A5 A6 A8 GND (Bank 1) ispMACH 5384B GLB/MC/Pad GND VCC VCCO (Bank 0) GND (Bank 0) K2 K0 L30 L22 L20 L18 L16 L14 L12 GND VCC VCCO (Bank 0) GND (Bank 0) L10 L8 L6 L4 L2 L0 NC NC GCLK0 GCLK1 TDI TMS TCK NC TDO VCC GND VCC GND A0 A2 A4 A6 A8 A10 GND (Bank 1) ispMACH 5512B GLB/MC/Pad GND VCC VCCO (Bank 0) GND (Bank 0) O18 O16 P30 P22 P20 P18 P16 P14 P12 GND VCC VCCO (Bank 0) GND (Bank 0) P10 P8 P6 P4 P2 P0 NC NC GCLK0 GCLK1 TDI TMS TCK NC TDO VCC GND VCC GND A0 A2 A4 A6 A8 A10 GND (Bank 1) Discontinued Product (PCN #02-06). Contact Rochester Electronics for Availability. www.latticesemi.com/sales/discontinueddevicessales.cfm 48 Lattice Semiconductor ispMACH 5000B Family Data Sheet ispMACH 5256B, 5384B, 5512B Logic Signal Connections: 256 fpBGA (Cont.) Ball Number M1 L3 L4 K5 M2 N1 K6 L5 N2 L6 L7 P1 P2 N3 R4 R1 T1 T2 R2 T3 R3 P4 T4 N4 M4 N5 R5 T5 T6 R6 P6 M5 Bank Number 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ispMACH 5256B GLB/MC/Pad VCCO (Bank 1) A10 A12 A14 A16 A18 A20 NC NC NC NC NC NC NC NC NC NC NC NC NC A21 A22 A24 A26 A28 A30 NC GND (Bank 1) VCCO (Bank 1) VCC GND NC NC NC NC NC NC NC NC NC NC NC B0 ispMACH 5384B GLB/MC/Pad VCCO (Bank 1) A12 A14 A16 A18 A20 A22 A26 A28 A30 B0 B2 GND VCC GND (Bank 1) VCCO (Bank 1) B4 B5 B6 B8 B12 B14 B16 B18 B20 B21 B22 GND (Bank 1) VCCO (Bank 1) VCC GND B24 B26 B28 B30 NC NC NC NC NC GND (Bank 1) VCCO (Bank 1) C0 ispMACH 5512B GLB/MC/Pad VCCO (Bank 1) A12 A14 A16 A18 A20 A22 A26 A28 A30 B0 B2 GND VCC GND (Bank 1) VCCO (Bank 1) B4 B5 B6 B8 B12 B14 B16 B18 B20 B21 B22 GND (Bank 1) VCCO (Bank 1) VCC GND B24 B26 B28 B30 C0 C2 C12 C16 C18 GND (Bank 1) VCCO (Bank 1) C20 Discontinued Product (PCN #02-06). Contact Rochester Electronics for Availability. www.latticesemi.com/sales/discontinueddevicessales.cfm 49 Lattice Semiconductor ispMACH 5000B Family Data Sheet ispMACH 5256B, 5384B, 5512B Logic Signal Connections: 256 fpBGA (Cont.) Ball Number T7 T8 R8 M6 N6 R7 T9 T10 M7 N7 P8 R9 N8 M8 T11 T12 R10 P9 R11 T13 N9 M9 R12 P11 N10 M10 R13 T14 R14 M11 N11 P13 T15 T16 N12 Bank Number 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 ispMACH 5256B GLB/MC/Pad B2 B4 B5 B6 B8 B10 B12 B14 B16/VREF1 B18 B20 GND (Bank 1) VCCO (Bank 1) VCC GND B21 B22 B24 B26 B28 B30 C0 C2 C4 C5 C6 C8 GND VCC VCCO (Bank 2) GND (Bank 2) C10 C12 C14 C16/VREF2 C18 C20 C21 C22 C24 C26 C28 C30 ispMACH 5384B GLB/MC/Pad C2 C4 C5 C6 C8 C10 C12 C14 C16/VREF1 C18 C20 GND (Bank 1) VCCO (Bank 1) VCC GND C21 C22 C24 C26 C28 C30 D0 D2 D4 D5 D6 D8 GND VCC VCCO (Bank 2) GND (Bank 2) D10 D12 D14 D16/VREF2 D18 D20 D21 D22 D24 D26 D28 D30 ispMACH 5512B GLB/MC/Pad C24 C26 C28 D0 D2 D4 D6 D8 D10/VREF1 D12 D16 GND (Bank 1) VCCO (Bank 1) VCC GND D18 D20 D22 D24 D26 D28 E0 E2 E4 E6 E8 E10 GND VCC VCCO (Bank 2) GND (Bank 2) E12 E16 E18 E20/VREF2 E22 E24 E26 E28 F0 F2 F4 F6 Discontinued Product (PCN #02-06). Contact Rochester Electronics for Availability. www.latticesemi.com/sales/discontinueddevicessales.cfm 50 Lattice Semiconductor ispMACH 5000B Family Data Sheet ispMACH 5256B, 5384B, 5512B Logic Signal Connections: 256 fpBGA (Cont.) Ball Number L10 L11 K11 R15 P15 R16 P16 N14 N13 N15 N16 M16 M12 M13 M15 L16 L15 L13 L14 L12 K13 K15 K16 J16 K12 J13 J14 J15 H15 Bank Number 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 ispMACH 5256B GLB/MC/Pad GND VCC VCCO (Bank 2) GND (Bank 2) NC NC NC NC NC NC NC D0 D2 NC NC NC NC D4 D5 D6 D8 D10 D12 D14 D16 D18 D20 VCCO (Bank 2) GND (Bank 2) D21 D22 D24 D26 D28 D30 GND VCC GND VCC TOE RESETB GOE0 GOE1 ispMACH 5384B GLB/MC/Pad GND VCC VCCO (Bank 2) GND (Bank 2) E4 E6 E8 E10 E18 E20 E22 E24 E26 VCCO (Bank 2) GND (Bank 2) VCC GND E28 E30 F0 F2 F8 F10 F12 F14 F16 F18 VCCO (Bank 2) GND (Bank 2) F20 F22 F24 F26 F28 F30 GND VCC GND VCC TOE RESETB GOE0 GOE1 ispMACH 5512B GLB/MC/Pad GND VCC VCCO (Bank 2) GND (Bank 2) G4 G6 G8 G10 G18 G20 G22 G24 G26 VCCO (Bank 2) GND (Bank 2) VCC GND G28 G30 H0 H2 H8 H10 H12 H14 H16 H18 VCCO (Bank 2) GND (Bank 2) H20 H22 H24 H26 H28 H30 GND VCC GND VCC TOE RESETB GOE0 GOE1 Discontinued Product (PCN #02-06). Contact Rochester Electronics for Availability. www.latticesemi.com/sales/discontinueddevicessales.cfm 51 Lattice Semiconductor ispMACH 5000B Family Data Sheet ispMACH 5256B, 5384B, 5512B Logic Signal Connections: 256 fpBGA (Cont.) Ball Number H14 H13 H16 J10 J12 G16 G15 H12 G12 G13 F16 F15 F13 F14 F12 E16 G11 F11 F10 B11 E13 B12 E15 D15 D16 E12 A16 B15 A15 D13 B14 B16 Bank Number 2 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 ispMACH 5256B GLB/MC/Pad GCLK2 GCLK3 NC NC E30 E28 E26 E24 E22 E21 GND (Bank 3) VCCO (Bank 3) VCC GND E20 E18 E16 E14 E12 E10 NC NC NC NC NC NC NC NC NC NC NC NC NC E8 E6 E5 E4 E2 E0 NC GND VCC GND (Bank 3) ispMACH 5384B GLB/MC/Pad GCLK2 GCLK3 NC NC G30 G28 G26 G24 G22 G20 GND (Bank 3) VCCO (Bank 3) VCC GND G18 G16 G14 G12 G10 G8 G6 G4 G2 G0 H30 H28 GND (Bank 3) VCCO (Bank 3) VCC GND H26 H24 H20 H18 H16 H14 H12 H10 H8 H6 GND VCC GND (Bank 3) ispMACH 5512B GLB/MC/Pad GCLK2 GCLK3 NC NC I30 I28 I26 I24 I22 I20 GND (Bank 3) VCCO (Bank 3) VCC GND I18 I16 I14 I12 I10 I8 I6 I4 I2 I0 J14 J12 GND (Bank 3) VCCO (Bank 3) VCC GND J10 J8 J2 J0 K30 K28 K26 K24 K22 K21 GND VCC GND (Bank 3) Discontinued Product (PCN #02-06). Contact Rochester Electronics for Availability. www.latticesemi.com/sales/discontinueddevicessales.cfm 52 Lattice Semiconductor ispMACH 5000B Family Data Sheet ispMACH 5256B, 5384B, 5512B Logic Signal Connections: 256 fpBGA (Cont.) Ball Number C16 C15 D14 A14 C13 B13 A13 A12 A11 A10 C11 A9 D12 D11 B10 B9 E11 A8 D10 E10 A7 C9 E9 D9 B8 A6 B7 C8 B6 A5 D8 E8 B5 Bank Number 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 0 0 0 0 0 0 ispMACH 5256B GLB/MC/Pad VCCO (Bank 3) NC NC NC NC NC NC VCC GND NC NC NC NC NC F30 F28 F26 F24 F22 F21 F20 F18 F16/VREF3 F14 F12 F10 GND (Bank 3) VCCO (Bank 3) VCC GND F8 F6 F5 F4 F2 F0 G30 G28 G26 G24 G22 G21 GND ispMACH 5384B GLB/MC/Pad VCCO (Bank 3) H5 H4 H2 H0 NC NC VCC GND NC NC NC GND (Bank 3) VCCO (Bank 3) I30 I28 I26 I24 I22 I21 I20 I18 I16/VREF3 I14 I12 I10 GND (Bank 3) VCCO (Bank 3) VCC GND I8 I6 I5 I4 I2 I0 J30 J28 J26 J24 J22 J21 GND ispMACH 5512B GLB/MC/Pad VCCO (Bank 3) K20 K18 K16 K14 K12 K10 VCC GND K4 K2 K0 GND (Bank 3) VCCO (Bank 3) L30 L28 L26 L24 L22 L21 L20 L18 L16/VREF3 L14 L12 L10 GND (Bank 3) VCCO (Bank 3) VCC GND L8 L6 L5 L4 L2 L0 M30 M28 M26 M24 M22 M21 GND Discontinued Product (PCN #02-06). Contact Rochester Electronics for Availability. www.latticesemi.com/sales/discontinueddevicessales.cfm 53 Lattice Semiconductor ispMACH 5000B Family Data Sheet ispMACH 5256B, 5384B, 5512B Logic Signal Connections: 256 fpBGA (Cont.) Ball Number A4 D7 E7 C6 B4 A3 D6 E6 A2 B3 C4 D5 Bank Number 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ispMACH 5256B GLB/MC/Pad VCC VCCO (Bank 0) GND (Bank 0) G20 G18 G16/VREF0 G14 G12 G10 G8 G6 G5 G4 G2 G0 GND VCC ispMACH 5384B GLB/MC/Pad VCC VCCO (Bank 0) GND (Bank 0) J20 J18 J16/VREF0 J14 J12 J10 J8 J6 J5 J4 J2 J0 GND VCC ispMACH 5512B GLB/MC/Pad VCC VCCO (Bank 0) GND (Bank 0) M20 M18 M16/VREF0 M14 M12 M10 M8 M6 M5 M4 M2 M0 GND VCC Discontinued Product (PCN #02-06). Contact Rochester Electronics for Availability. www.latticesemi.com/sales/discontinueddevicessales.cfm ispMACH 5512B Logic Signal Connections: 484 fpBGA Ball Number C2 C1 D1 D2 D3 E1 J1 K1 H3 J2 H4 K2 Bank Number 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ispMACH 5512B GLB/MC/Pad VCCO (Bank 0) GND (Bank 0) VCC GND N8 N6 N5 N4 N2 N0 VCCO (Bank 0) GND (Bank 0) O30 O28 O26 O24 O22 O20 GND VCC VCCO (Bank 0) 54 Lattice Semiconductor ispMACH 5000B Family Data Sheet ispMACH 5512B Logic Signal Connections: 484 fpBGA (Cont.) Ball Number J6 L1 K3 J4 L2 M1 K6 K4 L3 K5 N1 M2 P1 L4 N2 M3 L5 R1 P2 N3 M6 M5 M4 N4 N6 N5 P6 R6 R2 T1 R3 R4 Bank Number 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ispMACH 5512B GLB/MC/Pad GND (Bank 0) O18 O16 O14 O12 O10 O8 O6 O4 O2 O0 GND VCC VCCO (Bank 0) GND (Bank 0) P30 P28 P26 P24 P22 P20 P18 P16 P14 P12 GND VCC VCCO (Bank 0) GND (Bank 0) P10 P8 P6 P4 P2 P0 GCLK0 GCLK1 TDI TMS TCK TDO VCC GND Discontinued Product (PCN #02-06). Contact Rochester Electronics for Availability. www.latticesemi.com/sales/discontinueddevicessales.cfm 55 Lattice Semiconductor ispMACH 5000B Family Data Sheet ispMACH 5512B Logic Signal Connections: 484 fpBGA (Cont.) Ball Number R5 T2 T5 T3 U1 U4 V1 U3 V5 V2 W1 V3 W2 Y1 Y2 W3 AA3 W4 W5 Y4 T6 Y5 U6 AA4 W6 V4 U7 AB2 V7 AA5 Bank Number 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ispMACH 5512B GLB/MC/Pad VCC GND VCC GND A0 A2 A4 A6 A8 A10 GND (Bank 1) VCCO (Bank 1) A12 A14 A16 A18 A20 A22 A24 A26 A28 A30 B0 B2 GND VCC GND (Bank 1) VCCO (Bank 1) B4 B5 B6 B8 B10 B12 B14 B16 B18 B20 B21 B22 GND (Bank 1) VCCO (Bank 1) VCC Discontinued Product (PCN #02-06). Contact Rochester Electronics for Availability. www.latticesemi.com/sales/discontinueddevicessales.cfm 56 Lattice Semiconductor ispMACH 5000B Family Data Sheet ispMACH 5512B Logic Signal Connections: 484 fpBGA (Cont.) Ball Number AB3 Y6 AB4 Y7 AB5 V8 AA7 Y8 AB6 W8 AA8 Y10 U8 AB7 U9 AA9 W9 AB8 U10 AB9 V11 AA10 V10 AB10 W10 W11 U11 AA11 V12 AB11 Bank Number 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ispMACH 5512B GLB/MC/Pad GND B24 B26 B28 B30 C0 C2 C4 C8 C10 C12 C16 C18 GND (Bank 1) VCCO (Bank 1) C20 C24 C26 C28 D0 D2 D4 D6 D8 D10/VREF1 D12 D16 GND (Bank 1) VCCO (Bank 1) VCC GND D18 D20 D22 D24 D26 D28 GND VCC VCC GND VCC GND Discontinued Product (PCN #02-06). Contact Rochester Electronics for Availability. www.latticesemi.com/sales/discontinueddevicessales.cfm 57 Lattice Semiconductor ispMACH 5000B Family Data Sheet ispMACH 5512B Logic Signal Connections: 484 fpBGA (Cont.) Ball Number W12 Y11 Y12 AB12 U12 AA12 Y13 AB13 W13 AA13 U13 AB14 V13 AA14 U14 AB15 Y15 AB16 AA15 W14 AB17 Y16 AA16 Y17 AB18 V15 AB19 W15 AB20 AA18 U15 W17 U16 Bank Number 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 ispMACH 5512B GLB/MC/Pad E0 E2 E4 E6 E8 E10 GND VCC VCCO (Bank 2) GND (Bank 2) E12 E16 E18 E20/VREF2 E22 E24 E26 E28 F0 F2 F4 F6 VCCO (Bank 2) GND (Bank 2) F8 F10 F12 F16 F18 F20 F22 F24 F26 F28 G0 G2 GND VCC VCCO (Bank 2) GND (Bank 2) G4 G6 G8 Discontinued Product (PCN #02-06). Contact Rochester Electronics for Availability. www.latticesemi.com/sales/discontinueddevicessales.cfm 58 Lattice Semiconductor ispMACH 5000B Family Data Sheet ispMACH 5512B Logic Signal Connections: 484 fpBGA (Cont.) Ball Number AA19 V16 AB21 Y18 W18 AA20 W19 Y19 V19 Y21 W20 AA22 W21 Y22 V20 V21 W22 V18 U20 V22 U19 U17 U22 T20 T21 T17 R20 T18 R19 R18 R17 Bank Number 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 ispMACH 5512B GLB/MC/Pad G10 G12 G14 G16 G18 G20 G22 G24 G26 VCCO (Bank 2) GND (Bank 2) VCC GND G28 G30 H0 H2 H4 H6 H8 H10 H12 H14 H16 H18 VCCO (Bank 2) GND (Bank 2) H20 H22 H24 H26 H28 H30 GND VCC GND VCC GND VCC TOE RESETB GOE0 GOE1 Discontinued Product (PCN #02-06). Contact Rochester Electronics for Availability. www.latticesemi.com/sales/discontinueddevicessales.cfm 59 Lattice Semiconductor ispMACH 5000B Family Data Sheet ispMACH 5512B Logic Signal Connections: 484 fpBGA (Cont.) Ball Number P17 P19 R21 T22 P21 N20 R22 N21 M18 N19 P22 M20 N22 N17 M19 M21 L19 L20 M17 M22 K20 L18 L21 K19 L22 K17 K22 L17 K21 K18 J17 Bank Number 2 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 ispMACH 5512B GLB/MC/Pad GCLK2 GCLK3 I30 I28 I26 I24 I22 I20 GND (Bank 3) VCCO (Bank 3) VCC GND I18 I16 I14 I12 I10 I8 I6 I4 I2 I0 GND (Bank 3) VCCO (Bank 3) VCC GND J30 J28 J26 J24 J22 J20 J18 J16 J14 J12 GND (Bank 3) VCCO (Bank 3) VCC GND J10 J8 J6 Discontinued Product (PCN #02-06). Contact Rochester Electronics for Availability. www.latticesemi.com/sales/discontinueddevicessales.cfm 60 Lattice Semiconductor ispMACH 5000B Family Data Sheet ispMACH 5512B Logic Signal Connections: 484 fpBGA (Cont.) Ball Number J19 J22 J21 F22 E22 E19 E20 D22 D21 D20 C22 C18 C19 D17 C21 B16 D14 A18 F15 A17 B15 A16 F14 C15 D13 E15 F13 B14 E13 Bank Number 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 ispMACH 5512B GLB/MC/Pad J4 J2 J0 GND (Bank 3) VCCO (Bank 3) K30 K28 K26 K24 K22 K21 GND VCC GND (Bank 3) VCCO (Bank 3) K20 K18 K16 K14 K12 K10 GND (Bank 3) VCCO (Bank 3) GND (Bank 3) VCCO (Bank 3) VCC GND K8 K6 K5 K4 K2 K0 GND (Bank 3) VCCO (Bank 3) L30 L28 L26 L24 L22 L21 L20 L18 Discontinued Product (PCN #02-06). Contact Rochester Electronics for Availability. www.latticesemi.com/sales/discontinueddevicessales.cfm 61 Lattice Semiconductor ispMACH 5000B Family Data Sheet ispMACH 5512B Logic Signal Connections: 484 fpBGA (Cont.) Ball Number A15 D12 A14 B13 A13 B12 C13 A12 C12 A11 D11 B11 E12 C11 F12 B10 A10 D10 A9 E11 B9 F11 E8 A5 F8 C6 D8 A3 Bank Number 3 3 3 3 3 3 3 3 3 3 3 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ispMACH 5512B GLB/MC/Pad L16/VREF3 L14 L12 L10 GND (Bank 3) VCCO (Bank 3) VCC GND L8 L6 L5 L4 L2 L0 GND VCC GND VCC VCC GND M30 M28 M26 M24 M22 M21 GND VCC VCCO (Bank 0) GND (Bank 0) M20 M18 M16/VREF0 M14 M12 M10 M8 M6 M5 M4 M2 M0 GND Discontinued Product (PCN #02-06). Contact Rochester Electronics for Availability. www.latticesemi.com/sales/discontinueddevicessales.cfm 62 Lattice Semiconductor ispMACH 5000B Family Data Sheet ispMACH 5512B Logic Signal Connections: 484 fpBGA (Cont.) Ball Number A2 A4 F7 C5 F6 B3 B4 D5 B1 D6 C4 E4 Bank Number 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ispMACH 5512B GLB/MC/Pad VCC VCCO (Bank 0) GND (Bank 0) N30 N28 N26 N24 N22 N21 VCCO (Bank 0) GND (Bank 0) N20 N18 N16 N14 N12 N10 Discontinued Product (PCN #02-06). Contact Rochester Electronics for Availability. www.latticesemi.com/sales/discontinueddevicessales.cfm 63 Lattice Semiconductor ispMACH 5000B Family Data Sheet Part Number Description LC XXXXB - XX X XXX X Device Family Device Number 5128 = 128 Macrocells 5256 = 256 Macrocells 5384 = 384 Macrocells 5512 = 512 Macrocells Supply Voltage B = 2.5V Speed 3 = 3.0ns 4 = 4.0ns 45 = 4.5ns 5 = 5.0ns 75 = 7.5ns 10 = 10ns 12 = 12ns Grade C = Commercial I = Industrial Pin/Ball Count 128 208 256 484 Package T = TQFP Q = PQFP F = fpBGA 0212/ispm5b Discontinued Product (PCN #02-06). Contact Rochester Electronics for Availability. www.latticesemi.com/sales/discontinueddevicessales.cfm Ordering Information Commercial Device LC5128B Part Number LC5128B-3T128C LC5128B-5T128C LC5128B-75T128C LC5256B-4T128C LC5256B-4Q208C LC5256B-4F256C LC5256B-5T128C LC5256B LC5256B-5Q208C LC5256B-5F256C LC5256B-75T128C LC5256B-75Q208C LC5256B-75F256C LC5384B-4Q208C LC5384B-4F256C LC5384B LC5384B-5Q208C LC5384B-5F256C LC5384B-75Q208C LC5384B-75F256C Macrocells 128 128 128 256 256 256 256 256 256 256 256 256 384 384 384 384 384 384 Voltage 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 tPD 3.0 5.0 7.5 4.0 4.0 4.0 5.0 5.0 5.0 7.5 7.5 7.5 4.0 4.0 5.0 5.0 7.5 7.5 Package TQFP TQFP TQFP TQFP PQFP fpBGA TQFP PQFP fpBGA TQFP PQFP fpBGA PQFP fpBGA PQFP fpBGA PQFP fpBGA Pin/Ball Count 128 128 128 128 208 256 128 208 256 128 208 256 208 256 208 256 208 256 I/O 92 92 92 92 144 144 92 144 144 92 144 144 156 186 156 186 156 186 Grade C C C C C C C C C C C C C C C C C C 64 Lattice Semiconductor Commercial (Cont.) Device Part Number LC5512B-45Q208C LC5512B-45F256C LC5512B-45F484C LC5512B-75Q208C LC5512B LC5512B-75F256C LC5512B-75F484C LC5512B-10Q208C LC5512B-10F256C LC5512B-10F484C Macrocells 512 512 512 512 512 512 512 512 512 Voltage 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 ispMACH 5000B Family Data Sheet Discontinued Product (PCN #02-06). Contact Rochester Electronics for Availability. www.latticesemi.com/sales/discontinueddevicessales.cfm tPD 4.5 4.5 4.5 7.5 7.5 7.5 10 10 10 Package PQFP fpBGA fpBGA PQFP fpBGA fpBGA PQFP fpBGA fpBGA Pin/Ball Count 208 256 484 208 256 484 208 256 484 I/O 156 196 256 156 196 256 156 196 256 Grade C C C C C C C C C Note: The speed grade for these devices are dual marked. For example, the commercial grade -4xxxxC is also marked with the industrial grade -5xxxxI. The commercial grade is always one speed grade faster than the associated dual mark industrial grade. Industrial Device LC5128B Part Number LC5128B-5T128I LC5128B-75T128I LC5128B-10T128I LC5256B-5T128I LC5256B-5Q208I LC5256B-5F256I LC5256B-75T128I LC5256B LC5256B-75Q208I LC5256B-75F256I LC5256B-10T128I LC5256B-10Q208I LC5256B-10F256I LC5384B-5Q208I LC5384B-5F256I LC5384B LC5384B-75Q208I LC5384B-75F256I LC5384B-10Q208I LC5384B-10F256I LC5512B-75Q208I LC5512B-75F256I LC5512B-75F484I LC5512B-10Q208I LC5512B LC5512B-10F256I LC5512B-10F484I LC5512B-12Q208I LC5512B-12F256I LC5512B-12F484I Macrocells 128 128 128 256 256 256 256 256 256 256 256 256 384 384 384 384 384 384 512 512 512 512 512 512 512 512 512 Voltage 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 tPD 5.0 7.5 10 5.0 5.0 5.0 7.5 7.5 7.5 10 10 10 5.0 5.0 7.5 7.5 10 10 7.5 7.5 7.5 10 10 10 12 12 12 Package TQFP TQFP TQFP TQFP PQFP fpBGA TQFP PQFP fpBGA TQFP PQFP fpBGA PQFP fpBGA PQFP fpBGA PQFP fpBGA PQFP fpBGA fpBGA PQFP fpBGA fpBGA PQFP fpBGA fpBGA Pin/Ball Count 128 128 128 128 208 256 128 208 256 128 208 256 208 256 208 256 208 256 208 256 484 208 256 484 208 256 484 I/O 92 92 92 92 144 144 92 144 144 92 144 144 156 186 156 186 156 186 156 196 256 156 196 256 156 196 256 Grade I I I I I I I I I I I I I I I I I I I I I I I I I I I Note: The speed grade for these devices are dual marked. For example, the commercial grade -4xxxxC is also marked with the industrial grade -5xxxxI. The commercial grade is always one speed grade faster than the associated dual mark industrial grade. 65 Lattice Semiconductor ispMACH 5000B Family Data Sheet For Further Information In addition to this data sheet, the following technical notes may be helpful when designing with the ispMACH 5000B family: * sysIO Design and Usage Guidelines (TN1000) * Power Estimation in ispMACH 5000B Devices (TN1023) Discontinued Product (PCN #02-06). Contact Rochester Electronics for Availability. www.latticesemi.com/sales/discontinueddevicessales.cfm 66 |
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